Low-voltage analog IC design in CMOS technology

Coban, A.L.; Allen, P.E.; Shi, Xudong

doi:10.1109/81.477206

Cited by 30 publications

(11 citation statements)

References 8 publications

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“…This shows that the circuit is capable of low voltage operation and hence low power consumption of the circuit can be achieved. This low voltage operation of the proposed circuit is due to the use of single stacked transistor along with a memristor connected load unlike the other low voltage mode multipliers that use double stacked transistors [4][5] [19]. Thus, it can be operated at a voltage as low as ±0.3V with moderate linearity.…”

Section: Low Voltage Operation and Reduced Power Consumptionmentioning

confidence: 96%

Reconfigurable Memristor and CNFET based Four Quadrant Multiplier for Low Power Applications

Kafeel¹,

Zulqarnain²,

Hasan³

2017

IJCA

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In this paper, a reconfigurable, low power four quadrant memristor and carbon nanotube field effect Transistor (CNFET) based analog multiplier is proposed. The circuit is verified by extensive HSPICE simulations using experimentally verified memristor and Stanford CNFET models that have been calibrated for 90% accuracy at the 32nm technology node. The proposed multiplier has an input range of ±0.25V, extremely large bandwidth of 30.5 GHz, and consumes just 43.8μW of power along with low total harmonic distortion (THD% ≤0.75) and significant noise suppression at a supply voltage of ±0.3V.

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Section: Low Voltage Operation and Reduced Power Consumptionmentioning

confidence: 96%

Reconfigurable Memristor and CNFET based Four Quadrant Multiplier for Low Power Applications

Kafeel¹,

Zulqarnain²,

Hasan³

2017

IJCA

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“…To avoid transconductance and slew-rate variations when both of the input pairs operate, a feed-forward cancellation circuit is used in this design increasing the power consumption. The designs [1][2][3][4][5][6] require at least 2 V supply voltage.…”

Section: Introductionmentioning

confidence: 99%

“…The conventional rail-to-rail input stage is based on complementary differential amplifier [1][2][3][4][5] requiring some complexity to reach small variations of transconductance and slew-rate. Apart from few exceptions such as [4], this method assumes matching between input devices of different type which is difficult to achieve due to process parameters variations.…”

Section: Introductionmentioning

confidence: 99%

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Rail-to-rail BiCMOS operational amplifier using input signal adapters with floating outputs

Tadic

Banjevic

Schloegl

et al. 2009

Analog Integr Circ Sig Process

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An operational amplifier with rail-to-rail input and output voltage range in 0.6 lm BiCMOS technology is presented. Two simple input signal adapters with floating outputs serving as pre-stages are introduced. They are followed by a differential amplifier. The adapters translate the input signals into a floating level within the operating region of the differential amplifier, enabling rail-to-rail operation. An inverter-based simple rail-to-rail class AB output stage has been used. With a single supply of 1.5 V, the proposed rail-to-rail operational amplifier achieves 72 dB DC open-loop gain, 2.54 MHz unity-gain frequency, 62°phase margin, 2.5 V/ls slew rate, and 147 lW power consumption.

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“…The differential input pair used in opamps and OTAs has an inherent limitation of reduced input common-mode range (CMR) [1]. This problem can be avoided with parallel-connected complementary differential pairs in the input stage [2], but this method sets a minimum requirement on the supply voltage, limiting its application to supply voltages in the order of 3 V. In addition, this technique results in a varying opamp transconductance depending on the input common-mode (CM) voltage, and therefore extra circuits are necessary to keep the transconductance constant [3]. There are several other techniques to obtain a rail-to-rail input CM swing.…”

mentioning

confidence: 99%