Low-voltage CMOS programmable gain amplifier for UHF applications

Calvo, B.; Celma, S.; Aznar, Francisco; Alegre, J.P.

doi:10.1049/el:20071140

Cited by 17 publications

(6 citation statements)

References 4 publications

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“…There exist mainly two topologies for the implementation of the PGA: the negative feedback closed-loop architecture [ 2 ] and the open-loop architectures [ 9 , 10 ]. The gain of the closed-loop PGA is dependent on the ratio of the feedback resistance to the input resistance and is insensitive to PVT variations.…”

Section: Introductionmentioning

confidence: 99%

“…However, implementing such a PGA demands an op-amp with an extremely high gain and sometimes also requires a wide bandwidth which means that a power hungry op-amp is needed. On the other hand, open-loop PGAs implement the programmable gain by using the variable input transconductance [ 9 ] or output load [ 10 ], and the requirements on op-amps are quite relaxed. However, open-loop PGAs suffer a lot from PVT variations.…”

Section: Introductionmentioning

confidence: 99%

“…For example, the THD performance in reference [ 11 ] is only about −50 dB and is not suitable for some applications requiring high linearity. Traditional resistive feedback PGAs are still widely employed in the cases [ 8 , 9 , 16 , 17 ]. However, the linearity of the traditional closed-loop resistive feedback PGAs is limited by the nonidealities of the MOS switches utilized in the feedback resistor array network.…”

Section: Introductionmentioning

confidence: 99%

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Linearity Enhancement Techniques for PGA Design

Wang

Wan

et al. 2023

Micromachines

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This paper presents some techniques to improve the linearity of traditional resistive feedback PGAs. By utilizing the switched op-amp in the PGA, the MOS switches in the feedback resistor array can be eliminated and thus the PGA’s linearity can be improved. The PGA’s linearity is further improved with an additional capacitor, which is used for pre-charging the sampling capacitor to strengthen its capability to drive the sampling capacitor without any extra power consumption. The pre-charge technique is especially suitable for the case where the PGA drives a large sampling capacitance. Implemented in SMIC 0.18 um CMOS technology, the proposed PGA can achieve a gain of 0.5 or 1 and consumes 4.68 mW at a single 5 V supply with the switched output stage enabled. When driving a 20 pF sampling capacitor at a sampling frequency of 200 kHz, the simulation results show that the proposed PGA can give a 9 dBc improvement in SFDR of the sampled signal compared to the traditional PGA design and the SFDR can reach up to 114 dBc.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Linearity Enhancement Techniques for PGA Design

Wang

Wan

et al. 2023

Micromachines

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“…According to our survey, the VGA/PGA circuits presented so far in open literature were supplied with relatively large voltages, ranging from 1 V for ULP biomedical circuits [7], to several volts for high-frequency VGAs devoted to communication receivers [8][9][10][11][12][13][14][15][16][17][18][19][20][21][22]. Their architectures are rather not suitable for sub 0.5-V supply, because such a low supply voltage imposes specific design constraints and challenges.…”

Section: Introductionmentioning

confidence: 99%

0.3‐V bulk‐driven programmable gain amplifier in 0.18‐µm CMOS

Kulej

Khateb

2016

Circuit Theory & Apps

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A new solution for an ultra low voltage bulk-driven programmable gain amplifier (PGA) is described in the paper. While implemented in a standard n-well 0.18-μm complementary metal-oxide-semiconductor (CMOS) process, the circuit operates from 0.3 V supply, and its voltage gain can be regulated from 0 to 18 dB with 6-dB steps. At minimum gain, the PGA offers nearly rail-to-rail input/output swing and the input referred thermal noise of 2.37 μV/Hz 1/2 , which results in a 63-dB dynamic range (DR). Besides, the total power consumption is 96 nW, the signal bandwidth is 2.95 kHz at 5-pF load capacitance and the thirdorder input intercept point (IIP 3 ) is 1.62 V. The circuit performance was simulated with LTspice. Copyright

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“…However, although resistive feedback amplifiers usually provide high linearity, they are not suitable for high-frequency applications due to the large current required by high-frequency operational amplifiers. For highfrequency applications, open-loop amplifiers using the variable input g m [6] or output loads [7], as shown in Fig. 1(c) and (d), respectively, are popular.…”

Section: Introductionmentioning

confidence: 99%

A Binary-Weighted Switching and Reconfiguration-Based Programmable Gain Amplifier

Nguyen

Lee

et al. 2009

IEEE Trans. Circuits Syst. II

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In previous works, the authors reported on binaryweighted switching and reconfiguration techniques to design programmable gain amplifiers (PGAs) with a wide decibel (dB)-linear range, a small gain error, a wide 3-dB bandwidth, and high linearity. In this brief, two techniques are analyzed in more detail. Adopting the two techniques, a new low-voltage PGA version is proposed that offers a precise and process/temperature-insensitive gain and achieves a double dB-linear range with a small gain error while maintaining the same chip size, as compared with those of previous designs. Implemented in 0.18-μm CMOS, from the measurements, the proposed PGA shows a dB-linear gain range of 42 dB (−21 to 21 dB) with a gain error of less than ±0.54 dB, a maximum input-referred third-order intercept point (IIP3) of 14 dBm, and a 3-dB bandwidth of 60 MHz at the maximum gain while consuming only 2.1 mA from a 1.5-V supply.Index Terms-Decibel (dB)-linear gain, digitally controlled variable-gain amplifier (VGA), programmable gain amplifier (PGA), reconfiguration.

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Low-voltage CMOS programmable gain amplifier for UHF applications

Cited by 17 publications

References 4 publications

Linearity Enhancement Techniques for PGA Design

Linearity Enhancement Techniques for PGA Design

0.3‐V bulk‐driven programmable gain amplifier in 0.18‐µm CMOS

A Binary-Weighted Switching and Reconfiguration-Based Programmable Gain Amplifier

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