Low-Voltage Embedded NAND-ROM Macros Using Data-Aware Sensing Reference Scheme for VDDmin, Speed and Power Improvement

Yang, Shu-Meng; Chang, Meng‐Fan; Chiang, Chi-Chuang; Chen, Ming-Pin; Yamauchi, Hiroyuki

doi:10.1109/jssc.2012.2229068

Cited by 10 publications

(2 citation statements)

References 40 publications

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“…However, the variability in the reference and strobe signals necessitates timing margins, which degrades the performance. The issue in generating reference signal can be resolved by the data aware sensing reference scheme which adjusts the reference input according to data voltage [13]. However, the structure still suffers from the strobe signal variation.…”

Section: Introductionmentioning

confidence: 99%

Switching pMOS Sense Amplifier for High-Density Low-Voltage Single-Ended SRAM

Jeong

Kim

Kang

et al. 2015

IEEE Trans. Circuits Syst. I

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A switching pMOS sense amplifier (SPSA) is proposed for high-speed single-ended static RAM sensing. By using the same pull-up pMOS transistor for sensing and precharging the bit-line, the performance is enhanced, and the power consumption is reduced. A keeper that compensates bit-line leakage is also employed, and a minimum operating voltage of 0.51 V is obtained. Compared to the previous dynamic pMOS sense amplifier and AC-coupled sense amplifier (ACSA), the sensing time is improved by 55% and 10%, respectively, and the power consumption is reduced by 12% and 44%, respectively. Furthermore, the area of the SPSA is estimated to be 43% smaller than that of the ACSA. Although the SPSA has a 59% larger area than a dynamic pMOS sense amplifier, the area overhead can be mitigated by allocating a larger number of cells per bit-line (CpBL) because the performance of the SPSA is still better than that of the dynamic pMOS, even with a CpBL that is two times larger.Index Terms-AC-coupled sense amplifier, high-speed sensing amplifier, single-ended static RAM (SRAM), SRAM sensing.

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Section: Introductionmentioning

confidence: 99%

Switching pMOS Sense Amplifier for High-Density Low-Voltage Single-Ended SRAM

Jeong

Kim

Kang

et al. 2015

IEEE Trans. Circuits Syst. I

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“…Previous works [4][5] address VDIFF reductions due to bit-line leakage and bit-line coupling. These techniques [5][6] are useful for deep sub-threshold design where supply noise concern is relatively very low. The impact of power mesh ringing has not been explored to a large extent.…”

Section: Introductionmentioning

confidence: 99%

A CMOS 90nm 50Mhz Supply Noise Tolerant High Density 8T-NAND ROM

Dhori

Kumar

2015

2015 28th International Conference on VLSI Design

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On-chip power grid design is a major challenge in submicron technologies. High peak current coupled with inductive reactance of supply mesh results in power integrity issue results in ringing. This supply noise reduces the available differential voltage for sensing and results in read failure in Read only memory (ROM). Controlling the noise by using large decoupling capacitor is area consuming. Proposed scheme uses a noise tolerant reference generation. Scheme reduces the coupling effect of noise on differential nodes at Sense Amplifier. This is done by decoupling the differential nodes from power supply noise using highly capacitive shared reference lines. Thus, the impact of supply noise on differential voltage is reduced by ~90%. Scheme results in improvement in speed and power by 20% and 5% respectively with no area loss. We achieved 50MHz operating frequency with 8T-NAND High VT (HVT) ROM for 8192x128 (i.e. 8K words and 128 bits) instance.

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