2015
DOI: 10.1109/tcsi.2015.2415171
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Switching pMOS Sense Amplifier for High-Density Low-Voltage Single-Ended SRAM

Abstract: A switching pMOS sense amplifier (SPSA) is proposed for high-speed single-ended static RAM sensing. By using the same pull-up pMOS transistor for sensing and precharging the bit-line, the performance is enhanced, and the power consumption is reduced. A keeper that compensates bit-line leakage is also employed, and a minimum operating voltage of 0.51 V is obtained. Compared to the previous dynamic pMOS sense amplifier and AC-coupled sense amplifier (ACSA), the sensing time is improved by 55% and 10%, respective… Show more

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Cited by 15 publications
(2 citation statements)
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“…The removal of such access transistor allows for an area savings up to 20-30% compared to the conventional 6T SRAM cell, while its power consumption is substantially reduced by one half [15]. Although the conventional 5T SRAM cells offer such significant reduction in power consumption, a critical drawback is shown that in SRAM cells configured with single-ended bit line, whenever a write operation is performed, a write failure may occur [16][17]. In particular, it is relatively difficult to write a logical '1' to a cell if the cell currently stores a logical '0'.…”
Section: Conventional 5t Sram Cellmentioning
confidence: 99%
“…The removal of such access transistor allows for an area savings up to 20-30% compared to the conventional 6T SRAM cell, while its power consumption is substantially reduced by one half [15]. Although the conventional 5T SRAM cells offer such significant reduction in power consumption, a critical drawback is shown that in SRAM cells configured with single-ended bit line, whenever a write operation is performed, a write failure may occur [16][17]. In particular, it is relatively difficult to write a logical '1' to a cell if the cell currently stores a logical '0'.…”
Section: Conventional 5t Sram Cellmentioning
confidence: 99%
“…In 65-nm CMOS technology with various operational modes, the usefulness of body biasing in lowering offset is examined. The DIBBSA with floating output nodes (DIBBSA-FL) / DIBBSA with predischarge output nodes (DIBBSA-PD) works consistently at 0.4 VDD from 0 to 75 degrees C. In low-voltage planner CMOS SRAMs, DIBBSA-FL/PD can replace standard SAs [ 7 , 8 , 9 , 10 ]. For our proposed design, the negative wordline technique was used to improve power consumption.…”
Section: Introductionmentioning
confidence: 99%