Low-voltage-swing logic circuits for a 7GHz x86 integer core

Deleganes, D.J.; Barany, Micah; Geannopoulos, G.; Kreitzer, K.C.; Singh, A.P.; Wijeratne, S.

doi:10.1109/isscc.2004.1332640

Cited by 15 publications

(7 citation statements)

References 2 publications

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“…Increasing V dd is not the only way to increase the clock frequency. The LPH microarchitecture can be specifically designed for high clock frequency by implementing long pipelines and by shortening critical paths, using latches and flip-flops optimized for speed, dynamic logic, low-Vt transistors, low-voltage swing logic [7], etc. 4 ILP techniques will be important too, especially for latency tolerance (large instruction window, complex branch predictor, complex cache prefetcher, etc.).…”

Section: The Sequential Acceleratormentioning

confidence: 99%

Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache misses

Michaud

Sazeides

Seznec

2010

Proceedings of the 7th ACM International Conference on Computing Frontiers

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As the number of transistors on a chip doubles with every technology generation, the number of on-chip cores also increases rapidly, making possible in a foreseeable future to design processors featuring hundreds of general-purpose cores. However, though a large number of cores speeds up parallel code sections, Amdahl's law requires speeding up sequential sections too. We argue that it will become possible to dedicate a substantial fraction of the chip area and power budget to achieve high sequential performance. Current general-purpose processors contain a handful of cores designed to be continuously active and run in parallel. This leads to power and thermal constraints that limit the core's performance. We propose removing these constraints with a sequential accelerator (SACC). A SACC consists of several cores designed for ultimate sequential performance. These cores cannot run continuously. A single core is active at any time, the rest of the cores are inactive and power-gated. We migrate the execution periodically to another core to spread heat generation uniformly over the whole SACC area, thus addressing the temperature issue. The SACC will be viable only if it yields significant sequential performance. Migration-induced cache misses may limit performance gains. We propose some solutions to mitigate this problem. We also investigate a migration method using thermal sensors, such that the migration interval depends on the ambient temperature and the migration penalty is negligible under normal thermal conditions.

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Section: The Sequential Acceleratormentioning

confidence: 99%

Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache misses

Michaud

Sazeides

Seznec

2010

Proceedings of the 7th ACM International Conference on Computing Frontiers

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“…By pipelin ing and subsequent voltage scaling can minimize energy dis sipation at a given operation frequency with the conventional static CMOS, however, the energy and delay overhead of pipeline becomes so significant that all the system efficiency is degraded. To solve this issue, technologies such as low threshold voltage circuits [1], [2], low voltage swing logic [3] and charge-recovery circuits are developed.…”

Section: Introductionmentioning

confidence: 99%

A novel structure of energy efficiency charge recovery logic

Zhang

Okamura

Huang

et al. 2010

The 2010 International Conference on Green Circuits and Systems

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A novel charge-recovery logic structure called Pulse Boost Logic (PBL) is proposed in this paper. PBL is a high speed low-energy-dissipation charge-recovery logic with dual-rail evaluation tree structure. It is driven by 2-phase non-overlap clock, and requires no DC power supply. To demonstrate the performance of PBL structure, 4-bit counters designed with both PBL gates and conventional static CMOS. Post-layout simulation is applied to compare energy dissipation performance between PBL and conventional static CMOS in a frequency range of 500MHz to IGHz. The simulation result indicates that PBL dissipates only 15% energy per cycle at IGHz, and for sequential circuits such as counter, PBL is less area consuming than static CMOS.

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“…As clock frequency increases, clock skew, pipeline overhead, large wire delay are eating a significant portion of the cycle time, leaving very stringent room for logic operations. This scenario is especially true for designing high-end microprocessor integer cores, which are required to operate at twice of the system clock rate [1], [2]. Moreover, high clock frequency imposes great challenges on power budgeting, as power increases linearly with the clock rate.…”

Section: Introductionmentioning

confidence: 99%

High performance current-mode differential logic

Zhang¹,

Liu²,

Zhu³

et al. 2008

2008 Asia and South Pacific Design Automation Conference

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This paper presents a new logic style, named Current-Mode Differential logic (CMDL), that achieves both high operating speed and low power consumption. Inspired by the low-voltage swing (LVS) logic, CMDL uses a shunt resistor at the differential output to obtain constant low swing signal without the need to reset low. Furthermore, conditional shunt transistors are used for the internal nodes to prevent high-voltage swing, thus entirely eliminate the power-hungry clocked reset network in LVS circuits. We show that the CMDL is suitable for high-end microprocessor integer core by providing three datapath modules implemented in CMDL. Our simulation results indicate that, operating at comparable speed with LVS logic, CMDL circuits can achieve up to 50% reduction of delay-power product compared to CMOS logic and LVS logic. In addition, CMDL reduces the power consumption of LVS by up to 40%.

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Low-voltage-swing logic circuits for a 7GHz x86 integer core

Cited by 15 publications

References 2 publications

Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache misses

Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache misses

A novel structure of energy efficiency charge recovery logic

High performance current-mode differential logic

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