<title>Modulator-based multistage free-space optical interconnection system</title>

Abstract

We describe the design and implementation of a free-space optical interconnect for multi-processor and backplane applications. The system is designed to interconnect 4 nodes in a unidirectional ring, with a total of 256data channels propagating from node to node. Each node contains an array 5 12 GaAs electro-absorption modulators and 512 photodetectors, hybridly attached to a silicon integrated circuit. Light is relayed between nodes with a rigid micro-optical system. System results are presented.

Power complexity of multiplexer-based optoelectronic crossbar switches

“…After two iterations of mathematical analysis, the is determined to be 127 bits. This large value of will violate the vertical wire routing constraint in (16), and the area has been increased appropriately. The chip area will be 343 mm ., the side length will be 18.5 mm, the aggregate throughput will be 5.13 Tb/s, and the power dissipation will be 26 W. This figure is for the crossbar switch alone, without the memory, arbitration logic, and optical I/O.…”

“…Multimode fiber has an attenuation of 3 dB/km [37], and 50 m of fiber ribbon will have an attenuation of 0.15 dB. Our proposed imaging system uses two optical lenses and one microlens array, each contributing 1-dB loss (similar to data reported in [16]). Allowing a further 3-dB loss for bending, aging, and temperature effects, the optical signal power at the receiver will be 9.6 dBm, or 110 W. The sensitivity of a PD, defined as the received signal power required to ensure a bit-error rate (BER) of 10 , is reported to be 16 dBm for similar GaAs PDs operating at 2 Gb/s [24].…”

“…The second summation reflects the lengths of the wires entering a multiplexer standard cell, expressed in multiples of the height of the subtree, assuming the destination standard cell is placed at the median height. For the worst-case tree, the total length of wires in a multiplexer tree is given by (14) Therefore, the total length of wires in the average-case tree is (15) Assuming all wires are long distance wires with a 6 width and 10 pitch, a worst-case assumption, then the following vertical wire routing constraint must also be recognized: the total area used to route vertical wires must be realizable on layers of metal given the area of the switch, i.e., (16) Our analysis indicates that this vertical wiring routing constraint is met for the 0.18-m CMOS process with six or more layers of metal, for switches of degree 2. However for degree 4 or 8 multiplexers, the area consumed by routing vertical wires increases, and this constraint may not be met, in which case the area of the switch must be increased until (16) holds.…”

“…The signals can be coupled into the fibers using a 32 48 array of polymer or diffractive microlenses. See [16] for a discussion of imaging techniques used to interconnect 512 free-space optical signals between OEICs, in a free-space optical backplane.…”

“…An essentially-nonblocking multistage crossbar switch architecture which scales to hundreds of terabits of capacity using OEIC technology was proposed in [15]. A ten-year Canadian project to design a free-space multiterabit optical backplane is described in [16], [17]. A multiterabit local area network (LAN) using optoelectronic crossbars is described in [18], and transistor-level switch designs for optoelectronic networks are considered in [19].…”