&lt;title&gt;Single-crystal micromachining using multiple fusion-bonded layers&lt;/title&gt;

Brown, Alan; O'Neill, G.L.; Blackstone, S.

doi:10.1117/12.396460

Cited by 5 publications

(3 citation statements)

References 7 publications

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“…The previous sections have concentrated on post processing of a standard SOl material but the bonding technique offers several interesting possibilities including pre processing and multi layer bonding (23). This pre bond processing may involve patterned or blanket implants, precavitation or patterning of the buried oxide.…”

Section: Processing Techniques and Resultsmentioning

confidence: 99%

<title>HARM processing techniques for MEMS and MOEMS devices using bonded SOI substrates and DRIE</title>

et al. 2000

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Silicon-on-Insulator (501) MEMS devices (1) are rapidly gaining popularity in realising numerous solutions for MEMS, especially in the optical and inertia application fields. BCO recently developed a DRIE trench etch, utilising the Bosch process, and refill process for high voltage dielectric isolation integrated circuits on thick SOT substrates (2,3,4). In this paper we present our most recently developed DRIE processes for MEMS and MOEMS devices. These advanced etch techniques are initially described and their integration with silicon bonding demonstrated. This has enabled process flows that are currently being utilised to develop optical router and filter products for fibre optics telecommunications and high precision accelerometers.SOT MEMS allows thicker structures, common with bulk micromachining, to be integrated with CMOS, as utilised in surface micromachining. The buried sacrificial oxide layer enables 3-D structures to be implemented in single crystal silicon which removes the stress associated with polysilicon. This offers substantial improvements in increased lateral sensitivity for inertia applications and it facilitates the removal of the perforated surface in MOEMS designs by etching through the handle wafer to release the mirrors.Although the Bosch process was the catalyst that allowed High Aspect Ratio Micromachining (HARM) products to be developed, processes have historically been restricted to bulk micromachining due to the lateral etch characteristics, at the buried oxide interface, for SOT substrates. Several 501 etch processes will be presented that clearly demonstrate the elimination of this notching effect. These applications will include multi feature 501 etching to oxide and through the wafer anisotropic etching.

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Section: Processing Techniques and Resultsmentioning

confidence: 99%

<title>HARM processing techniques for MEMS and MOEMS devices using bonded SOI substrates and DRIE</title>

et al. 2000

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“…The double-bonded SOI wafers are fabricated using fusion bonding and etch-back [6]. The devices are patterned using electron beam lithography.…”

Section: Device Fabricationmentioning

confidence: 99%

Silicon based double-layer 1×12 multimode interference coupler for three-dimensional photonic integration

Zhang

Hosseini

Ahn

et al. 2012

2012 Optical Interconnects Conference

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“…The double-bonded SOI wafers are fabricated using fusion bonding and etch-back, 21 one SF 6 /C 4 F 8 /Ar based deep reactive-ion-etching (DRIE) step in Plasma-Therm's Versaline system. The DRIE process consists of $1000 iterations of a two-step polymer deposition/etching cycle.…”

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confidence: 99%

Vertically integrated double-layer on-chip silicon membranes for 1-to-12 waveguide fanouts

Zhang

Hosseini

Ahn

et al. 2012

Applied Physics Letters

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<title>Single-crystal micromachining using multiple fusion-bonded layers</title>

Cited by 5 publications

References 7 publications

<title>HARM processing techniques for MEMS and MOEMS devices using bonded SOI substrates and DRIE</title>

<title>HARM processing techniques for MEMS and MOEMS devices using bonded SOI substrates and DRIE</title>

Silicon based double-layer 1×12 multimode interference coupler for three-dimensional photonic integration

Vertically integrated double-layer on-chip silicon membranes for 1-to-12 waveguide fanouts

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<title>Single-crystal micromachining using multiple fusion-bonded layers</title>

Cited by 5 publications

References 7 publications

<title>HARM processing techniques for MEMS and MOEMS devices using bonded SOI substrates and DRIE</title>

<title>HARM processing techniques for MEMS and MOEMS devices using bonded SOI substrates and DRIE</title>

Silicon based double-layer 1&#x00D7;12 multimode interference coupler for three-dimensional photonic integration

Vertically integrated double-layer on-chip silicon membranes for 1-to-12 waveguide fanouts

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Product

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Silicon based double-layer 1×12 multimode interference coupler for three-dimensional photonic integration