Maestro: A high performance AES encryption/decryption system

Biglari, Mehrdad; Qasemi, Ehsan; Pourmohseni, Behnaz

doi:10.1109/cads.2013.6714255

Cited by 7 publications

(3 citation statements)

References 1 publication

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“…In design [3], it achieves low-cost, but it doesn't support all 5 kinds of mode and have lower throughput than our design. Design proposed in [4] achieves higher throughput with respect to our design, but it takes much more resources than our design. The implementation in [5] is based on co-processor architecture, but it does not support all 5 modes and has lower throughput.…”

Section: Vmentioning

confidence: 79%

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An Implementation of Configurable and Small- Area AES IP Core Oriented Avalon Bus

Tao¹,

Zhang²,

Song³

2015

Advances in Intelligent Systems Research

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The Advanced Encryption Standard (AES) issued by the National Institute of Standards and Technology in 2001 has become the new widely-used symmetric block cipher standard. A lot of efforts have been made on the various hardware implementations of the AES algorithm. Some focus on achieving low-cost constructions, while others focus on designing high throughput. Given the specific requirement of wireless communication and portable devices, this article presents an AES IP core with an acceptable trade-off between performance and area. By introducing composite fields Sboxes and researching optimization of MixColumn can reduce resources. The AES IP is designed based on Avalon bus. It is compatible with five modes including ECB, CBC, OFB, CFB, and CTR. 128,196,256 bits key are also supported. Meanwhile, it can be flexibly configured according to the specific circumstances. This design and implementation of the AES core has a certain value for the generalization the wireless communication terminal hardware platform.

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Section: Vmentioning

confidence: 79%

“…In the designs [2] [3], the core is designed with Microblaze processor core. [4] [5] use Altera NIOS II core. In this paper, we propose an Advanced Encryption Standard (AES) based on Altera NIOS II core, implement the design and simulation of AES module compatible with five modes based on Avalon bus.…”

Section: Introductionmentioning

confidence: 99%

An Implementation of Configurable and Small- Area AES IP Core Oriented Avalon Bus

Tao¹,

Zhang²,

Song³

2015

Advances in Intelligent Systems Research

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“…A fully pipelined AES processor has more complex operations and achieves throughput between 30 and 70 Gbps [4]. A high performance AES system, by using a ten stage implicit pipelined architecture, the system performance is limited upto 1.85 Gbps because of the memory usage [5]. Implementation of a fully pipelined AES processor on FPGA which gave a performance of 21.54 Gbps but occupied a large area of 5177 slices and showed latency of 31 cycles [6].…”

Section: Related Workmentioning

confidence: 99%

FPGA implementation of efficient AES encryption

Priya

Kumar

Sivamangai

et al. 2015

2015 International Conference on Innovations in Information, Embedded and Communication Systems (ICIIECS)

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In this paper, a high throughput modified Advanced Encryption Standard (AES)-128 bit algorithm is implemented. A new increased parallelism technique is introduced in modified AES architecture in Mix Column round which increases the overall throughput of AES algorithm. This technique is implemented in XC5VLX50T FPGA device Virtex-5.Using this technique throughput is increased 5 % and area is decreased by 30 % when compared to parallel mixcolumn.

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