Majority logic circuits optimisation by node merging

Chung, Chun-Che; Chen, Yung-Chih; Wang, Chun-Yao; Wu, Chia-Cheng

doi:10.1109/aspdac.2017.7858408

Cited by 10 publications

(6 citation statements)

References 18 publications

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“…We compare our results to the state-of-the-art approach presented in [20], which we reimplemented using FR from Section 3 and windowing to achieve larger scalability and therefore address larger benchmarks. In our experiments, we found that the results obtained with our implementation of [20] outperform the more recently presented results in [6]; the latter can also easily be validated by comparing the numbers for size and depth in Table 2 from the previous section to [6, Table III] for the common benchmarks (i2c, max, square, log2, multiplier). Table 3 shows area, delay, energy, and the ADE product for each of the benchmarks when mapped to QCA and STMG technologies, respectively.…”

Section: Area-delay-energy Product Reduction For Qca and Stmgsupporting

confidence: 70%

“…The method has been extended to work with all 4-input subgraphs in [20]. A size optimization node merging approach, which removes node redundancies in MIGs, has been presented in [6].…”

Section: Mig Optimization Techniquesmentioning

confidence: 99%

“…Functional reduction (FR) [5,6,9] is an approach that identifies and merges functionally equivalent nodes in a logic network such that after its application no two nodes in the functionally reduced network represent the same logic function. In this section, we revise the basic functional reduction approach of [9] and present a scalable variant utilizing the windowing procedure from the previous section.…”

Section: Functional Reductionmentioning

confidence: 99%

See 2 more Smart Citations

Nonsilicon, Non-von Neumann Computing—Part I [Scanning the Issue]

Basu¹,

Bryant²,

Micheli³

et al. 2019

Proc. IEEE

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Majority-inverter graphs (MIGs) are a logic representation with remarkable algebraic and Boolean properties that enable efficient logic optimizations beyond the capabilities of traditional logic representations. Further, since many nano-emerging technologies, such as quantum-dot cellular automata (QCA) or spin torque majority gates (STMG), are inherently majority-based, MIGs serve as a natural logic representation to map into these technologies. So far, MIG optimization methods predominantly target to reduce the depth of the logic networks, corresponding to low delay implementations in the respective technologies. In this paper, we introduce several methods to optimize the size of MIGs. They can be applied such that the depth of the logic network is preserved; therefore our methods have a direct effect on the physical area, without worsening the delay. Some methods are inspired by existing size optimization algorithms for non-majority-based logic networks, others make explicit use of the majority function and its properties. All methods are Boolean-in contrast to algebraic optimization methods-which has a positive effect on the quality but challenges their implementation. Our experiments show that using our methods the size of MIGs in the EPFL combinational benchmark suite can be reduced by up to 7.12%. When mapped to QCA and STMG technologies we reduce the average area-delay-energy product by 2.31% and 2.07%, respectively.

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Section: Area-delay-energy Product Reduction For Qca and Stmgsupporting

confidence: 70%

“…The method has been extended to work with all 4-input subgraphs in [20]. A size optimization node merging approach, which removes node redundancies in MIGs, has been presented in [6].…”

Section: Mig Optimization Techniquesmentioning

confidence: 99%

Section: Functional Reductionmentioning

confidence: 99%

See 1 more Smart Citation

Nonsilicon, Non-von Neumann Computing—Part I [Scanning the Issue]

Basu¹,

Bryant²,

Micheli³

et al. 2019

Proc. IEEE

View full text Add to dashboard Cite

show abstract

“…A logic synthesis tool is proposed in [8], which takes any AND-OR-INVERT-based logic and synthesizes it purely in terms of majority and NOT gates. Boolean logic minimization techniques such as re-shaping, push-up, node merging, etc., are used to re-synthesize and optimize conventional AND-OR-INVERT logic in terms of MAJORITY-INVERT [33][34][35][36][37][38]. Since the majority is the fundamental logic primitive for many emerging nanotechnologies, there are also works which pioneered the synthesis of PP adders solely in terms of majority gates.…”

Section: Homogeneous Synthesis Of Parallel-prefix Addersmentioning

confidence: 99%

Design of In-Memory Parallel-Prefix Adders

Reuben

2021

JLPEA

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Computational methods in memory array are being researched in many emerging memory technologies to conquer the ‘von Neumann bottleneck’. Resistive RAM (ReRAM) is a non-volatile memory, which supports Boolean logic operation, and adders can be implemented as a sequence of Boolean operations in the memory. While many in-memory adders have recently been proposed, their latency is exorbitant for increasing bit-width (O(n)). Decades of research in computer arithmetic have proven parallel-prefix technique to be the fastest addition technique in conventional CMOS-based binary adders. This work endeavors to move parallel-prefix addition to the memory array to significantly minimize the latency of in-memory addition. Majority logic was chosen as the fundamental logic primitive and parallel-prefix adders synthesized in majority logic were mapped to the memory array using the proposed algorithm. The proposed algorithm can be used to map any parallel-prefix adder to a memory array and mapping is performed in such a way that the latency of addition is minimized. The proposed algorithm enables addition in O(log(n)) latency in the memory array.

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“…Although the logic realization of combinational circuits using the 3-input majority gate was proposed as early as the 1960's [19], [20], the latest nanometric technologies [21] have given rise to a renewed interest in synthesizing digital circuits using the majority gate and the inverter. Several digital electronic circuit synthesis and optimization techniques [22]- [27] have been proposed of late which utilize only the majority gate and the inverter as the basic building blocks. Also, logic synthesis schemes utilizing the minority gate and the inverter were proposed [23], [28], with the minority logic function being the complement of the majority logic function.…”

Section: Introductionmentioning

confidence: 99%

Mathematical estimation of logical masking capability of majority/minority gates used in nanoelectronic circuits

Balasubramanian

Naayagi

2017

2017 International Conference on Circuits, System and Simulation (ICCSS)

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Abstract-In nanoelectronic circuit synthesis, the majority gate and the inverter form the basic combinational logic primitives. This paper deduces the mathematical formulae to estimate the logical masking capability of majority gates, which are used extensively in nanoelectronic digital circuit synthesis. The mathematical formulae derived to evaluate the logical masking capability of majority gates holds well for minority gates, and a comparison with the logical masking capability of conventional gates such as NOT, AND/NAND, OR/NOR, and XOR/XNOR is provided. It is inferred from this research work that the logical masking capability of majority/minority gates is similar to that of XOR/XNOR gates, and with an increase of fan-in the logical masking capability of majority/minority gates also increases.

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Majority logic circuits optimisation by node merging

Cited by 10 publications

References 18 publications

Nonsilicon, Non-von Neumann Computing—Part I [Scanning the Issue]

Nonsilicon, Non-von Neumann Computing—Part I [Scanning the Issue]

Design of In-Memory Parallel-Prefix Adders

Mathematical estimation of logical masking capability of majority/minority gates used in nanoelectronic circuits

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