Management of Power and Performance with Stress Memorization Technique for 45nm CMOS

Eiho, A.; Sanuki, T.; Morifuji, E.; Iwamoto, Toshiyuki; Sudo, G.; Fukasaku, K.; Ota, Ken‐ichiro; Sawada, Takeshi; Fuji, O.; Nii, H.; Togo, M.; Ohno, Kohei; Yoshida, Kenji; Tsuda, Hiroshi; Ito, Toshio; Shiozaki, Yoichi; Fuji, Nobuo; Yamazaki, Hiroto; Nakazawa, M.; Iwasa, S.; Muramatsu, S.; Nagaoka, K.; Iwai, M.; Ikeda, Masayuki; Saito, Mikiko; Naruse, H.; Enomoto, Y.; Kitano,; Yamada, Shigeru; Imai, K.; Nishida, Naoki; Kuwata, T.; Matsuoka, F.

doi:10.1109/vlsit.2007.4339699

Cited by 11 publications

(9 citation statements)

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“…This result is similar to the data demonstrated in previous studies on SMT. 7 The poly-Si shows a smaller grain size after processing SMT. The gate leakage of stacked, random poly-Si gate structure is comparable to single poly-Si gate, which is near 0.7 pA/m for device length/ width of 10/0.4 m. The dependence of the channel-hot-carrier reliability is shown in Fig.…”

Section: Resultsmentioning

confidence: 97%

“…[1][2][3][4] Recently, the stress-memorization technique ͑SMT͒ has been reported to enhance electron mobility on n-channel metal-oxide semiconductor field effect transistors ͑nMOSFETs͒ and widely studied by different methods. [5][6][7] However, most previous studies have demonstrated the performance boost without considering the scalability of the gate density. As the scaling of design rules such as polypitch shrinks in high-density static random access memory circuits ͑as shown on the top of Fig.…”

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confidence: 99%

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Enhancement of Stress-Memorization Technique on nMOSFETs by Multiple Strain-Gate Engineering

Wang

Chao

2009

Electrochem. Solid-State Lett.

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An enhanced stress memorization-technique that utilizes a strain proximity free technique ͑SPFT͒ and a stacked-gate structure has been demonstrated by multiple strain-gate engineering. The electron mobility of n-channel metal-oxide semiconductor field effect transistors ͑nMOSFETs͒ with SPFT exhibit a 16% increase compared to that of counterpart techniques. SPFT avoids the limitation of stressor volume for performance improvement in high-density complementary metal oxide semiconductor circuits. We also found that optimization of stacked, random poly-Si-grain gate structure in combination with SPFT can improve mobility further to 22% more than a single poly-Si gate structure without SPFT.In pursuit of high-speed circuit applications, mobility enhancement by local stressor engineering in high-performance complementary metal oxide semiconductor ͑CMOS͒ transistors has been intensively studied using techniques such as dual-contact etch stop layer ͑DCESL͒ and embedded SiGe in the source/drain ͑S/D͒ area. 1-4 Recently, the stress-memorization technique ͑SMT͒ has been reported to enhance electron mobility on n-channel metal-oxide semiconductor field effect transistors ͑nMOSFETs͒ and widely studied by different methods. 5-7 However, most previous studies have demonstrated the performance boost without considering the scalability of the gate density. As the scaling of design rules such as polypitch shrinks in high-density static random access memory circuits ͑as shown on the top of Fig. 1͒, mobility enhancement is limited by stressor-volume and process-integration issues. Introducing longitudinal tensile stress and vertical compressive stress into the channel region are the well known principles of mobility enhancement on nMOSFETs. 8 However, longitudinal tensile stress is limited as the stressor volume reaches its saturation point, causing performance degradation. 9 Moreover, poor Ni-silicide formation and contact process integration issues are induced by stressor residue in highdensity CMOS circuits.In this work, we proposed a strain proximity free technique ͑SPFT͒ to avoid the limitation of stressor volume for performance improvement in high-density CMOS circuits. Stacked a-Si/poly-Si gate structure has been reported to enhance channel stress and electron mobility. 10 We also demonstrated that the stacked gate structure with optimization of a bottom layer of random poly-Si-grain size and thickness can further improve nMOSFET performance. ExperimentalnMOSFETs were fabricated on 6 in. wafers with resistivity of 15-25 ⍀ cm. After the RCA cleaning process, 2.5 Ϯ 0.1 nm gate oxide was grown in a vertical furnace ͑800°C, O 2 ambient͒. Then, the stacked-gate structure was built using poly-Si with optimization of bottom-layer poly-Si grain size and thickness and deposited in the same ambient. The bottom-layer thickness of the stacked gate is near 70 nm. The final gate thickness was kept the same for all samples at 200 nm. The SPFT, whose process flow is illustrated in Fig. 1, is proposed in order to introduce stress into the cha...

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Section: Resultsmentioning

confidence: 97%

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confidence: 99%

Enhancement of Stress-Memorization Technique on nMOSFETs by Multiple Strain-Gate Engineering

Wang

Chao

2009

Electrochem. Solid-State Lett.

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“…This could be originated from the different tensile strain. It has been reported that tensile strain from an SMT is obvious, specifically at the gate edge [6], [11]. Therefore, it is reasonable to deduce that the anomalously high gate tunneling current in Sample A is a result of higher tensile strain.…”

Section: Resultsmentioning

confidence: 91%

“…However, the change of strain will make a great impact on the gate tunneling current [1] tion of gate tunneling current by introducing the tensile strain in N-type metal-oxide-semiconductor field-effect transistor (NMOSFET) [2], [6]. In the course of boosting NMOSFET mobility using SMT with high tensile strain, the gate tunneling current was also found to be increased at the same time.…”

Section: Introductionmentioning

confidence: 99%

Anomalous Gate-Edge Leakage Induced by High Tensile Stress in NMOSFET

Liu

Huang

Lim

et al. 2008

IEEE Electron Device Lett.

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Anomalously high gate tunneling current, induced by high-tensile-stress memorization technique, is reported in this letter. Carrier-separation measurement method shows that the increased gate tunneling current is originated from the higher gate-to-source/drain (S/D) tunneling current, which worsens when channel length is getting shorter. Also, the device with enhanced tensile strain exhibits 9% higher gate-to-S/D overlapping capacitance. These data indicate that the anomalously high gate tunneling current could be attributed to the high tensile strain that induces the effects of excessive lightly doped dopant diffusion and higher gate-edge damage. The proposed inference is confirmed by channel hot-electron stress.Index Terms-Gate leakage current, MOSFETs, stress memorization technique (SMT).

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“…This compressive stress of n-type poly-Si gate then induces a tensile strain in nMOS channel along the longitudinal direction, as illustrated in Figure 5. Several factors can affect the benefit of SMT, including poly amorphorization implant, thickness and rigidity of the high-stress capping layer, and change of capping layer stress before and after hightemperature anneal [22,24,25]. Although in most cases degradation to pMOS is avoided through capping layer removal prior to the high-temperature anneal, it has been reported that the density of SiN used for capping layer can be modified to reduce, or even eliminate the pMOS degradation without going through additional steps of capping layer removal [26].…”

Section: Stress Memorization Technique (Smt)mentioning

confidence: 99%

Advanced strain engineering for state-of-the-art nanoscale CMOS technology

Yang

Cai

2011

Sci. China Inf. Sci.

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The introduction and advancement of strain engineering has been one of the most critical features for the state-of-the-art nanoscale CMOS transistors. This paper provides an overview of the major strain engineering techniques that have remarkably re-shaped the advanced CMOS transistor architecture, including embedded SiGe (eSiGe), embedded Si:C (eSi:C), stress memorization technique (SMT), dual stress liners (DSL), and stress proximity technique (SPT). The advent of high-K/metal-gate (HKMG) also brings in additional strain benefit with its metal gate stressor (MGS) and replacement gate (RMG) process. Strain engineering continues to evolve and will remain to be one of the key performance enablers for the future generation of CMOS technologies. CitationYang B, Cai M. Advanced strain engineering for state-of-the-art nanoscale CMOS technology. Sci China Inf Sci, 2011, 54: 946-958,

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Management of Power and Performance with Stress Memorization Technique for 45nm CMOS

Cited by 11 publications

References 0 publications

Enhancement of Stress-Memorization Technique on nMOSFETs by Multiple Strain-Gate Engineering

Enhancement of Stress-Memorization Technique on nMOSFETs by Multiple Strain-Gate Engineering

Anomalous Gate-Edge Leakage Induced by High Tensile Stress in NMOSFET

Advanced strain engineering for state-of-the-art nanoscale CMOS technology

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