Manufacturability study of masks created by inverse lithography technology (ILT)

Martin, Patrick; Progler, Christopher J.; Xiao, Gao; Gray, Rick; Pang, L.; Liu, Y.

doi:10.1117/12.633200

Cited by 12 publications

(9 citation statements)

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“…The Luminescent ILT, which was the pioneering product first introduced in 2005/2006, [9][10][11][12][13][14][15][16][17] tried to solve the ILT runtime problem by reducing the number of variables using the level-set method. It also provides a mathematically elegant method for solving topology discontinuity during ILT optimization.…”

Section: Luminescent Level-set Methodsmentioning

confidence: 99%

“…Six papers were presented by Luminescent 9,10 and its partners and customers, including UMC and Xilinx, 11 Cypress, 12 SMIC, 13 and Photronics. 14 The author of this ILT review paper, at that time working for Luminescent, was the first to formally name this method "inverse lithography technology" or "ILT," an acronym now universally used by the semiconductor industry. At SPIE Microlithography 2006, Luminescent CTO Dan Abrams and the author presented the milestone paper "Fast Inverse Lithography Technology," 15 along with other joint papers with its customers.…”

Section: History Of Inverse Lithographymentioning

confidence: 99%

“…The seeds for ILT were sown as early as the 1980s, with academic work. 1,2 By the 1990s, industrial research and development teams had started to work on ILT technologies that could be used in production, [3][4][5][6][7][8] with the first ILT product introduction in 2005/2006, [9][10][11][12][13][14][15][16][17] when the author first coined the term ILT. At this time, dry-process 45-nm lithography was the leading-edge target and was very challenging in terms of process window.…”

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confidence: 99%

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Inverse lithography technology: 30 years from concept to practical, full-chip reality

Pang

2021

J. Micro/Nanopattern. Mats. Metro.

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In lithography, optical proximity and process bias/effects need to be corrected to achieve the best wafer print. Efforts to correct for these effects started with a simple bias, adding a hammer head in line-ends to prevent line-end shortening. This first-generation correction was called rule-based optical proximity correction (OPC). Then, as chip feature sizes continued to shrink, OPC became more complicated and evolved to a model-based approach. Some extra patterns were added to masks, to improve the wafer process window, a measure of resilience to manufacturing variation. Around this time, the concept of inverse lithography technology (ILT), a mathematically rigorous inverse approach that determines the mask shapes that will produce the desired on-wafer results, was introduced. ILT has been explored and developed over the last three decades as the next generation of OPC, promising a solution to several challenges of advanced-node lithography, whether optical or extreme ultraviolet (EUV). Today, both OPC and ILT are part of an arsenal of lithography technologies called resolution enhancement technologies. Since OPC and ILT both involve computation, they are also considered as part of computational lithography. We explore the background and history of ILT and detail the significant milestones that have taken full-chip ILT from an academic concept to a practical production reality.

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Section: Luminescent Level-set Methodsmentioning

confidence: 99%

Section: History Of Inverse Lithographymentioning

confidence: 99%

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confidence: 99%

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Inverse lithography technology: 30 years from concept to practical, full-chip reality

Pang

2021

J. Micro/Nanopattern. Mats. Metro.

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“…1 Many researchers have studied to develop more advanced OPC methodology, 2-3 Among the various OPC methodologies, inverse lithography technique (ILT) is another methodology to obtain perfect patterns demanded in wafer level. The ideal mask shape is numerically derived from inverse transformation of the desired wafer pattern, [4][5] thus the ideal solution is composed of the curvilinear line.…”

Section: Introductionmentioning

confidence: 99%

Requirements of the e-beam shot quality for mask patterning of the sub-1X device

Park

Lee

et al. 2016

SPIE Proceedings

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As the integration node becomes smaller in 193nm ArF immersion optical lithography, the complexity of optical proximity correction (OPC) has been increased continuously. Moreover, pattern design should be changed by more aggressive transformation technique such as inverse lithography technique (ILT). The greater fidelity to the target design on wafers is achieved by the application of these OPC techniques and results in the greater complexity level of the mask patterns. Complicated mask pattern consists of many corners and assist features, which raises the fraction of small shots in e-beam data. To get more accurate mask pattern, the dose stability of small shots becomes more important in a complicated mask pattern.In this paper, we present the evaluation results of the small shot handling capabilities of e-beam machines. According to the results, the information of small shots generated during data fracturing should be considered as a factor that defines the complexity of patterns in e-beam writing. It shows that the small shot printing in e-beam machines need to be improved in order to guarantee mask pattern quality.

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“…Those are double patterning (DPT), EUV, source mask optimization (SMO), inverse lithography (ILT) and so on. Each technology requires tight CD and image placement control of mask due to aggressive OPC application and importance of mask registration and overlay accuracy [1,2,3,4]. Fig.1 shows ITRS roadmap for lithography technology and Table.1 shows mask requirements [5].…”

Section: Introductionmentioning

confidence: 99%

The requirements for the future e-beam mask writer: statistical analysis of pattern accuracy

et al. 2011

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As semiconductor features shrink in size and pitch, the extreme control of CD uniformity, MTT and image placement is needed for mask fabrication with e-beam lithography. Among the many sources of CD and image placement error, the error resulting from e-beam mask writer becomes more important than before. CD and positioning error by e-beam mask writer is mainly related to the imperfection of e-beam deflection accuracy in optic system and the charging and contamination of column. To avoid these errors, the e-beam mask writer should be designed taking into account for these effects. However, the writing speed is considered for machine design with the highest priority, because the e-beam shot count is increased rapidly due to design shrink and aggressive OPC. The increment of shot count can make the pattern shift problem due to statistical issue resulting from e-beam deflection error and the total shot count in layout. And it affects the quality of CD and image placement too.In this report, the statistical approach on CD and image placement error caused by e-beam shot position error is presented. It is estimated for various writing conditions including the intrinsic e-beam positioning error of VSB writer. From the simulation study, the required e-beam shot position accuracy to avoid pattern shift problem in 22nm node and beyond is estimated taking into account for total shot count. And the required local CD uniformity is calculated for various e-beam writing conditions. The image placement error is also simulated for various conditions including e-beam writing field position error. Consequently, the requirements for the future e-beam mask writer and the writing conditions are discussed. And in terms of e-beam shot noise, LER caused by exposure dose and shot position error is studied for future e-beam mask writing for 22nm node and beyond.

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Manufacturability study of masks created by inverse lithography technology (ILT)

Cited by 12 publications

References 0 publications

Inverse lithography technology: 30 years from concept to practical, full-chip reality

Inverse lithography technology: 30 years from concept to practical, full-chip reality

Requirements of the e-beam shot quality for mask patterning of the sub-1X device

The requirements for the future e-beam mask writer: statistical analysis of pattern accuracy

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