Manufacturing pattern development for the Alpha 21164 microprocessor

Stolicny, C.; Davies, Robert L.; McKernan, P.; Truong, Trieu‐Kien

doi:10.1109/test.1997.639628

Cited by 8 publications

(2 citation statements)

References 6 publications

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“…The tests done are typically used for checking the functionality of the system, but not for detecting manufacturing defects. Functional validation suites have been used regularly to perform manufacturing testing of processors [18]. However, its application relies on external testers and its results in terms of manufacturing fault coverage are low, as the validation suites are not targeted at structural faults.…”

Section: Introductionmentioning

confidence: 99%

Software-based self-testing methodology for processor cores

Chen

Dey

2001

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

189

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At-speed testing of gigahertz processors using external testers may not be technically and economically feasible. Hence, there is an emerging need for low-cost high-quality self-test methodologies that can be used by processors to test themselves at-speed. Currently, built-in self-test (BIST) is the primary self-test methodology available. While memory BIST is commonly used for testing embedded memory cores, complex logic designs such as microprocessors are rarely tested with logic BIST. In this paper, we first analyze the issues associated with current hardware-based logic-BIST methodologies by applying a commercial logic-BIST tool to two processor cores. We then propose a new software-based self-testing methodology for processors, which uses a software tester embedded in the processor memory as a vehicle for applying structural tests. The software tester consists of programs for test generation and test application. Prior to the test, structural tests are prepared for processor components in the form of self-test signatures. During the process of self-test, the test generation program expands the self-test signatures into test sets and the test application program applies the tests to the components under test at the speed of the processor. Application of the novel software-based self-test method demonstrates its significant cost/fault coverage benefits and its ability to apply at-speed test while alleviating the need for high-speed testers.

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Section: Introductionmentioning

confidence: 99%

Software-based self-testing methodology for processor cores

Chen

Dey

2001

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

189

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“…Implementing at-speed functional test using simulation waveforms has been proposed to recreate the customers' environment on automatic test equipment (ATE) [17,18]. However, high-functionality ICs having asynchronous clock domains require expensive ATE that can provide multiple asynchronous clocks during test.…”

Section: Introductionmentioning

confidence: 99%

At-Speed Structural Test For High-Performance ASICs

Iyengar

Yokota²,

Yamada³

et al. 2006

2006 IEEE International Test Conference

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At-speed test of integrated circuits is becoming critical to detect subtle delay defects. Existing structural at-speed test methods are inadequate because they are unable to supply sufficiently-varied functional clock sequences to test complex sequential logic. Moreover, they require tight restrictions on the circuit design. In this paper, we present a new method for at-speed structural test of ASICs, having no tight restrictions on the circuit design. In the present implementation, any complex at-speed functional clock waveform for 16 cycles can be applied. We present DFT structures that can generate high-speed launch-off-capture as well as launch-offscan clocking without the need to switch a scan enable atspeed. We also describe a method to test asynchronous clock domains simultaneously. Experimental results on fault coverage and hardware measurements for three multi-million gate ASICs demonstrate the feasibility of the proposed approach.

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