Mapping of PRP/HSR redundancy protocols onto a configurable FPGA/CPU based architecture

Abstract

This paper presents the mapping of the seamless redundancy protocols PRP and HSR in combination with IEEE 1588 based clock synchronization onto a configurable CPU/FPGA based Redundancy Box architecture. Whereas core functions of PRP, HSR, and IEEE 1588 are mapped onto the FPGA, a CPU executes the control parts of these protocols. An optional attached standard switch ASIC provides direct connection to several network devices. For validation purpose, a special embedded platform is proposed that is composed of an FPGA and a commercial off-the-shelf switch ASIC. The results show that even a low-cost Altera Cyclone IV FPGA comprising 74,000 logic elements fulfills the requirements for protocol processing at 100 Mbps per port. Minimum size frames are forwarded by the FPGA up to two times faster than competitive implementations. Three connected PRP/HSR RedBoxes and an IEEE 1588 clock master are synchronizing in laboratory within an accuracy of 30 ns. Using several RedBoxes in PRP and HSR mode, a seamless redundancy is demonstrated for a PROFINET RT test network and supplemental network components. Overall, the presented RedBox can be flexibly integrated into time-synchronized industrial networks in order to significantly increase the communication reliability

Exploiting multicore processors in PLCs using libraries for IEC 61131-3

“…A combination of a single processor with FPGA extension is demonstrated in [10]. This solution greatly increases the performance of an implementation in the FPGA part, while keeping the capability of general purpose computation.…”