Mapping of two-dimensional convolution on very long instruction word media processors for real-time performance

Abstract

Programmable media processors have been emerging to meet the continuously increasing computational demand in complex digital media applications, such as HDTV and MPEG-4, at an affordable cost. These media processors provide the flexibility to implement various image computing algorithms along with high performance, unlike the hardwired approach that has provided high performance for a particular algorithm, but lacks flexibility. However, to achieve high performance on these media processors, a careful and sometimes innovative design of algorithms is essential. In addition, programming techniques, e.g., software pipelining and loop unrolling, are needed to speed up the computations while the data flow can be optimized using a programmable DMA controller. In this paper, we describe an algorithm for two-dimensional convolution, which can be implemented efficiently on many media processors. Implemented on a new media processor called the MAP1000, it takes 7.9 ms to convolve a 512ϫ512 image with a 7ϫ7 kernel, which is much faster than the previously reported software-based convolution and is comparable with the hardwired implementations. High performance in two-dimensional convolution and other algorithms on the MAP1000 clearly demonstrates the feasibility of software-based solutions in demanding imaging and video applications. © 2000 SPIE and IS&T. [S1017-9909(00)

<title>Fast unsharp masking on a programmable mediaprocessor</title>

“…While the core processor computes on the data in the current cache block, the DMA controller stores the previously computed block into external memory and brings the next block to be processed from external memory to on-chip memory, thus overlapping the time required to move the data with the computing time. Details of using the DMA controller can be found in [14]. This example illustrates the computational advantage of using boxcar kernels compared to using generalized kernels, especially for the case requiring large kernels/low cutoff frequencies.…”

“…For each point in the output image, a total of M 2 -1 additions must be performed. An efficient moving average method [14,19] …”

“…Example mediaprocessors are TTI TriMedia, Texas Instruments TMS320C64x, Hitachi/Equator Technologies MAP-CA, and Intel Pentium 4. By optimally mapping the algorithm to the underlying processor architecture, high performance can be achieved [14,15]. In addition to high performance, these mediaprocessors can be programmed in C with intrinsics and provide smart compilers for higher software development productivity.…”

Real‐time video postprocessing for deblocking and deringing on mediaprocessors

“…The IGALU also supports powerful instructions for filtering operations used extensively in image and video applications. For example, a single inner-product instruction can perform eight 16-bit multiplications in parallel, summing the results into a 32-bit output (Managuli et al, 2000). The two clusters together are capable of executing 4 different instructions (e.g., 2 on IALUs and 2 on IGALUs) in each clock cycle.…”

<title>Media processor programming interface to increase the portability of media processor software</title>

“…Data flow programming in mediaprocessors is typically handled in two ways: programmable DMA (direct memory access) engines and cache prefetching [7]. Implementing data flow using a DMA engine involves software development around the core computation tight loop.…”