March test algorithm for unlinked static reduced three-cell coupling faults in random-access memories

Caşcaval, Petru; Caşcaval, Dan

doi:10.1016/j.mejo.2019.104619

Cited by 8 publications

(11 citation statements)

References 7 publications

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“…However, we produced this technique both to test and repair the memories for SoC-based devices. The fault test has been covered in the research [ 22 , 23 , 24 , 25 ] to test the embedded memory for faults. The stuck-at fault, transition fault, address decoder fault, and coupling faults are computed.…”

Section: Discussionmentioning

confidence: 99%

“…The March c and March c+ algorithms discussed in the research [ 25 ] enhance the fault coverage by presenting the March Y algorithm for memory in the study. This March Y algorithm can detect the stuck-at fault, transition fault, address decoder fault, and some coupling faults, whereas the memory test approaches presented [ 23 , 24 ] are not enough to catch all coupling faults. The March SS is given in the research [ 22 ] to compute the faults, and it detects SAF, TF, ADF, and some CFs with a comparatively high area overhead.…”

Section: Discussionmentioning

confidence: 99%

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Optimal Method for Test and Repair Memories Using Redundancy Mechanism for SoC

Alnatheer

Ahmed

2021

Micromachines

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The current system-on-chip (SoC)-based devices uses embedded memories of enormous size. Most of these systems’ area is dense with memories and promotes different types of faults appearance in memory. The memory faults become a severe issue when they affect the yield of the product. A memory-test and -repair scheme is an attractive solution to tackle this kind of problem. The built-in self-repair (BISR) scheme is a prominent method to handle this issue. The BISR scheme is widely used to repair the defective memories for an SoC-based system. It uses a built-in redundancy analysis (BIRA) circuit to allocate the redundancy when defects appear in the memory. The data are accessed from the redundancy allocation when the faulty memory is operative. Thus, this BIRA scheme affects the area overhead for the BISR circuit when it integrates to the SoC. The spare row and spare column–based BISR method is proposed to receive the optimal repair rate with a low area overhead. It tests the memories for almost all the fault types and repairs the memory by using spare rows and columns. The proposed BISR block’s performance was measured for the optimal repair rate and the area overhead. The area overhead, timing, and repair rate were compared with the other approaches. Furthermore, the study noticed that the repair rate and area overhead would increase by increasing the spare-row/column allocation.

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Section: Discussionmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%

Optimal Method for Test and Repair Memories Using Redundancy Mechanism for SoC

Alnatheer

Ahmed

2021

Micromachines

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“…e system framework of pattern recognition is shown in Figure 2, and the whole process is completed based on field-programmable gate array (FPGA) [14]. To be specific, the inherent static random access memory (SRAM) [15] is used to extract the roller tracks.…”

Section: Pattern Recognitionmentioning

confidence: 99%

Pattern Recognition and Neural Network-Driven Roller Track Analysis via 5G Network

Guo

2020

Mobile Information Systems

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Roller skating is an important and international physical exercise, which has beautiful body movements to be watched. However, the falling of roller athletes also happens frequently. Upon the roller athletes’ fall, it means that the whole competition is over and even the roller athletes are perhaps injured. In order to stave off the tragedy, the roller track can be analyzed and be notified the roller athlete to terminate the competition. With such consideration, this paper analyzes the roller track by using two advanced technologies, i.e., pattern recognition and neural network, in which each roller athlete is equipped with an automatic movement identifier (AMI). Meanwhile, AMI is connected with the remote video monitor referee via the transmission of 5G network. In terms of AMI, its function is realized by pattern recognition, including data collection module, data processing module, and data storage module. Among them, the data storage module considers the data classification based on roller track. In addition, the neural network is used to train the roller tracks stored at AMI and give the further analysis results for the remote video monitor referee. Based on NS3, the devised AMI is simulated and the experimental results reveal that the prediction accuracy can reach 100% and the analyzed results can be used for the falling prevention timely.

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“…Among the large variety of memory faults, coupling faults, CFs, involve two memory cells, a i and a j . The types of such faults are discussed below [3,[6][7][8][9].…”

Section: Introductionmentioning

confidence: 99%

“…They are still being developed with a time complexity that depends linearly on the memory capacity. Such tests are called march tests [1,3,[5][6][7][8][9][10] and are used for bit-oriented memory, where each cell stores one bit. A march test consists of a finite number of march elements [3].…”

Section: Introductionmentioning

confidence: 99%

Linked Coupling Faults Detection by Multirun March Tests

Mrozek,

Yarmolik

2024

Applied Sciences

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This paper addresses the problem of describing the complex linked coupling faults of memory devices and formulating the necessary and sufficient conditions for their detection. The main contribution of the proposed approach is based on using a new formal model of such faults, the critical element of which is the introduction of roles and scenarios performed by the cells involved in the fault. Three roles are defined such that the cells of the complex linked coupling faults perform, namely, the roles of the aggressor (A), the victim (V), and both (B), performed by two cells simultaneously in relation to each other. The memory march test and applied address sequence and background determine the scenario for implementing the roles of memory faulty cells. The necessary and sufficient conditions for detecting linked coupling faults are given based on a new formal model. Formally, the undetectable linked coupling faults are defined, and the conditions for their detection are formulated using multirun memory march tests. The experimental investigation confirmed the validity of the proposed formulated statements. Based on the example of a linked coupling fault, this study demonstrates the fulfillment of the necessary and sufficient conditions for its detection using a single march test. As demonstrated in this article, employing the approach proposed by the authors, a two-pass march C test, for instance, enables the attainment of 55.42% fault coverage for linked coupling faults, inclusive of undetectable faults identified by the single-pass march test.

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March test algorithm for unlinked static reduced three-cell coupling faults in random-access memories

Cited by 8 publications

References 7 publications

Optimal Method for Test and Repair Memories Using Redundancy Mechanism for SoC

Optimal Method for Test and Repair Memories Using Redundancy Mechanism for SoC

Pattern Recognition and Neural Network-Driven Roller Track Analysis via 5G Network

Linked Coupling Faults Detection by Multirun March Tests

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