Master-Slave TMR Inspired Technique for Fault Tolerance of SRAM-Based FPGA

Lahrach, Farid; Doumar, Abderrahim; Châtelet, Éric; Abdaoui, Abderrazek

doi:10.1109/isvlsi.2010.38

Cited by 8 publications

(2 citation statements)

References 11 publications

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“…A fine granularity approach to fault mitigation is presented in [144,145,146]. The presented method proposes the use of logic redundancy at the logic block level; in the case of a fault, small configuration activities can be undertaken to migrate logic from faulty regions (in essence a very fine grained form of relocation).…”

Section: Fault Mitigation Using Both Scrubbing and Relocationmentioning

confidence: 99%

A framework and method for the run-time on-chip synthesis of multi-mode self-organized reconfigurable stream processors

Dumitriu¹

2023

Preprint

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A number of modern digital processing systems implement complex multi-mode applications with high performance requirements and strict operating constraints; examples include video processing and telecommunication applications. A number of these systems use increasingly large FPGAs as the implementation medium, due to reduced development costs. The combination of increases in FPGA capacity and system complexity has lead to a non-linear increase in system implementation effort. If left unchecked, implementation effort for such systems will reach the point where it becomes a design and development bottleneck. At the same time, the reduction in transistor size used to manufacture these devices can lead to increased device fault rates. To address these two problems, the Multi-mode Adaptive Collaborative Reconfigurable self-Organized System (MACROS) Framework and design methodology is proposed and described in this work. The MACROS Framework other the ability for run-time architecture adaptation by integrating FPGA configuration into regular operation. The MACROS Framework allows for run-time generation of Application-Specific Processors (ASPs) through the deployment, assembly and integration of pre-built functional units; the framework further allows the relocation of functional units without affecting system functionality. The use of functional units as building blocks allows the system to be implemented on a piece-by-piece basis, which reduces the complexity of mapping, placement and routing tasks; the ability to relocate functional units allows fault mitigation by avoiding faulty regions in a device. The proposed framework has been used to implement multiple video processing systems which were used as verification and testing instruments. The MACROS framework was found to successfully support run-time architecture adaptation in the form of functional unit deployment and relocation in high performance systems. For large systems (more than 100 functional units), the MACROS Framework implementation effort, measured as time cost, was found to be one third that of a traditional (monolithic) system; more importantly, in MACRO Systems this time cost was found to increase linearly with system complexity (the number of functional units). When considering fault mitigation capabilities, the resource overhead associated with the MACROS Framework was found to be up to 85 % smaller than a traditional Triple Module Redundancy (TMR) solution.

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Section: Fault Mitigation Using Both Scrubbing and Relocationmentioning

confidence: 99%

A framework and method for the run-time on-chip synthesis of multi-mode self-organized reconfigurable stream processors

Dumitriu¹

2023

Preprint

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“…Formulation of major KPIs to gauge the effect of MIMO bi-directional converters and their support for FEW services as a collaborative FEW-Grid Resilience Index (CFGRI) using the KPIs presented in works [28,29] from the perspective of resilience in the energy efficiency of MIMO power drives communication systems.…”

Section: Smart Power Converters Kpismentioning

confidence: 99%

Multi-Channel Networked MIMO-MPC-based SiL/HiL/MiL for CC/CV Sections’ Optimization in 6th Gen Hybrid/Islanded Inverters for Mobile Green Nano-Grids in FEW Nexus

Tariq

Sultan

2022

International Journal on Applied Physics and Engineering

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The Food, Energy, and Water (FEW) Nexus is an ever-existing paradigm since the big bang. Resilient and mobile green energy nano-grid fabric is the horizon at the pinnacle of 6th generation inverters where FEW and major UNDP SDGs seem to meet. Three major challenges exist in the existing inverters: a) are based on uni-variable PID controllers and do not provide abstract grid parameters that make the decision-making for the consumers and OEMs, especially in islanded nano-grids; b) there is not a single MIMO-MPC-based solution that can employ a mesh network of spatially deployed Nanogrids nodes to derive the abstract key performance indicators (KPIs) in nano-grids, and c) the hardcoded smart inverters’ firmware is impossible to optimize like SoC-based SiL/MiL/MiL looped embedded systems that hamper the adaptation of SISO-MPC and MIMO-MPCs. In this work design, development, and optimization of multi-channel CC/CV section modules based on MIMO-MPC using Hardware in Loop (HiL), Software in Loop (SiL), and Model in Loop (MiL) integrated 6th generation inverters architecture was proposed to achieve the autonomous green mobility nano-girds. The system achieved an efficiency of 7.8kWh/day at 20.8ᵒ tilt with charging states of [23% to 65%].

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Dependability Threats

Bolchini¹,

Michael²,

Miele³

et al. 2017

Dependable Multicore Architectures at Nanoscale

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The increasing diversity, density, and complexity of electronic devices is enabling the so-called digital revolution with the evident pervasive presence of electronics in everybody's lives. The benefits of this ubiquitous presence are impressive and widespread: from the constant improvement of productivity in the workplace to the societal impact of a constantly connected and sharing community.Whatever is the considered scenario, all this incredible progress has been relying on the assumption that the devices can be depended on in their application and for their purposes. The foundations for this assumption are based on a constant work behind the scenes of the technical and scientific community aimed at enhancing the dependability of the devices.Dependability is a broad term that summarizes several aspects of a system, which typically include availability, reliability, maintainability, safety, and security. All these aspects define whether and how the system will behave according to several requirements which can have different levels of priority based on the specific application. In particular, availability measures the amount of time a system is readily operating, reliability measures the continuity of the correct service, maintainability shows the ability of the system of being repaired and/or modified, safety targets the avoidance of catastrophic consequences in the case of lack of service, and finally security targets the resilience of a systems to threats caused by malicious third parties.There is an impressive amount of examples from technical literature and from the news about the dreadful consequences of the lack of dependability of an electronic system. Lack of dependability may have several negative consequences spreading from the loss of reputation of a manufacturer to the catastrophic loss of lives. Consider for example the automotive scenario, several cases of massive recalls were caused by issues in the electronic system: famously in one of such cases it was speculated that unintended acceleration causing loss of lives was to be ascribed to faults occurring in the drive-by-wire control modules.Apart from the loss of lives, the economic impact of unreliable hardware must also be taken into account. Depending on the particular product and application domain, the costs associated to lack of dependability can be extremely high:xiii

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Master-Slave TMR Inspired Technique for Fault Tolerance of SRAM-Based FPGA

Cited by 8 publications

References 11 publications

A framework and method for the run-time on-chip synthesis of multi-mode self-organized reconfigurable stream processors

A framework and method for the run-time on-chip synthesis of multi-mode self-organized reconfigurable stream processors

Multi-Channel Networked MIMO-MPC-based SiL/HiL/MiL for CC/CV Sections’ Optimization in 6th Gen Hybrid/Islanded Inverters for Mobile Green Nano-Grids in FEW Nexus

Dependability Threats

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