Maximizing data reuse for minimizing memory space requirements and execution cycles

Abstract

Abstract-Embedded systems in the form of vehicles and mobile devices such as wireless phones, automatic banking machines and new multi-modal devices operate under tight memory and power constraints. Therefore, their performance demands must be balanced very well against their memory space requirements and power consumption. Automatic tools that can optimize for memory space utilization and performance are expected to be increasingly important in the future as increasingly larger portions of embedded designs are being implemented in software. In this paper, we describe a novel optimization framework that can be used in two different ways: (i) deciding a suitable on-chip memory capacity for a given code, and (ii) restructuring the application code to make better use of the available on-chip memory space. While prior proposals have addressed these two questions, the solutions proposed in this paper are very aggressive in extracting and exploiting all data reuse in the application code, restricted only by inherent data dependences.

Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organization

“…Complementing the cache system, scratch-pad memory (SPM) has been recently given attention. Approaches for dynamic management and allocation of cache and SPM have been seen in [28,29,30]. There exists some research works on buffering reused data in FPGA on-chip embedded RAMs and registers [31,32,33].…”

Energy-aware memory management for embedded multidimensional signal processing applications

“…The research on the assignment of signals (multidimensional arrays) to the memory layers [7] focused in part on how to restructure the application code to make better use of the available memory hierarchy [8]. Brockmeyer et al used the steering heuristic of assigning the arrays having the highest access number over size ratio to the cheapest memory layer, followed by incremental reassignments [9].…”