MBE HgCdTe on Si and GaAs substrates

Li, He; Chen, L.; Wu, Yan; Fu, Xiangliang; Wang, Y.Z.; Wu, Jun; Yu, Meifang; Yang, Junling; Ding, Rijun; Hu, Xiong-wei; Li, Y.J.; Zhang, Q.Y.

doi:10.1016/j.jcrysgro.2006.11.188

Cited by 40 publications

(20 citation statements)

References 13 publications

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“…2 Among these, Si and GaAs are the most promising, with tremendous progress having been made in recent years. 3,4 They are low cost and large area, and have many fewer surface defects compared with CdZnTe. Surface dislocation density values of Si, GaAs, and CdZnTe substrates are $100 cm À2 , $10 3 cm…”

Section: Introductionmentioning

confidence: 99%

Characterization of CdTe Growth on GaAs Using Different Etching Techniques

Bilgilisoy

Özden

Bakali

et al. 2015

Journal of Elec Materi

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CdTe buffer layers which were grown on (211)B GaAs by molecular beam epitaxy were subjected to two different etch treatments to quantify the crystal quality and dislocation density. The optical properties and thicknesses of the samples were obtained by ex situ spectroscopic ellipsometry. The surface morphologies of the CdTe epilayers were analyzed by atomic force microscopy, scanning electron microscopy, and Nomarski microscopy before and after chemical etching. We compare the triangle-and trapezoid-shaped etch pits due to the Everson and Nakagawa etch solutions, respectively. Measured etch pit density (EPD) values of triangle etch pits were found in the 8 9 10 7 cm À2 to 2 9 10 8 cm À2 range, and trapezoid-shaped etch pits were found in the 1 9 10 7 cm À2 to 7 9 10 7 cm À2 range for samples with thicknesses <2 lm.

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Section: Introductionmentioning

confidence: 99%

Characterization of CdTe Growth on GaAs Using Different Etching Techniques

Bilgilisoy

Özden

Bakali

et al. 2015

Journal of Elec Materi

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“…10,14 In addition, CdZnTe has a large difference in thermal expansion coefficient with flip-chip bonded complementary metal-oxide semiconductor (CMOS) readout circuits. 10,15 Thermal compatibility between the two materials is an important requirement, due to the cycling between room temperature and the low operation temperatures of HgCdTe infrared focal plane arrays (FPAs). 8,10,15 The interest in silicon (Si) as a potential substrate for HgCdTe has resulted in optimization of the quality of HgCdTe epitaxial films suitable for MWIR applications.…”

Section: Introductionmentioning

confidence: 99%

“…10,15 Thermal compatibility between the two materials is an important requirement, due to the cycling between room temperature and the low operation temperatures of HgCdTe infrared focal plane arrays (FPAs). 8,10,15 The interest in silicon (Si) as a potential substrate for HgCdTe has resulted in optimization of the quality of HgCdTe epitaxial films suitable for MWIR applications. 10,12 Si wafers are less expensive than CdTe and CdZnTe substrates, have higher structural integrity, and allow for the integration of Si readout circuitry for FPA structures.…”

Section: Introductionmentioning

confidence: 99%

“…10,12 Si wafers are less expensive than CdTe and CdZnTe substrates, have higher structural integrity, and allow for the integration of Si readout circuitry for FPA structures. [8][9][10]12,15,16 To overcome the 19% lattice mismatch between Si and HgCdTe, buffer layers are used to reduce the dislocation density associated with the misfit and to maintain the orientation of the substrate. 9,[11][12][13][15][16][17] A thin ZnTe (2-10 nm) buffer layer is grown on Si(211) substrates, followed by a thick (3-9 lm) layer of CdTe in the (211) orientation.…”

Section: Introductionmentioning

confidence: 99%

“…[8][9][10]12,15,16 To overcome the 19% lattice mismatch between Si and HgCdTe, buffer layers are used to reduce the dislocation density associated with the misfit and to maintain the orientation of the substrate. 9,[11][12][13][15][16][17] A thin ZnTe (2-10 nm) buffer layer is grown on Si(211) substrates, followed by a thick (3-9 lm) layer of CdTe in the (211) orientation. 16,18 The ability to maintain the (211) orientation during CdTe growth is critical, since this is thought to reduce the formation of twins on (111) surfaces.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Characterization of Smooth CdTe(111) Films by the Conventional Close-Spaced Sublimation Technique

Escobedo

Quinones

Adame

et al. 2010

Journal of Elec Materi

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Thin epitaxial CdTe films were grown on CdTe(111)B substrates by the close-spaced sublimation (CSS) technique and were characterized over a range of experimental parameters. The source temperature was varied between 480°C and 540°C, maintaining an average constant source-substrate temperature difference DT of $130°C. Helium was used as a carrier gas at pressures between 2 Torr and 10 Torr. Scanning electron microscopy (SEM) and x-ray diffraction (XRD) were used to analyze the film morphology and structure. Growth rates ranging from 1 lm/h to 4 lm/h were observed, based on profilometer thickness measurements. The addition of a pre-growth heat treatment step and post-growth annealing treatment resulted in smooth CdTe (111) films. An evolution in growth morphology was demonstrated with SEM images and film quality was confirmed with XRD.

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Substrates for the Epitaxial Growth of MCT

Garland

Sporken

2010

Mercury Cadmium Telluride

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MBE HgCdTe on Si and GaAs substrates

Cited by 40 publications

References 13 publications

Characterization of CdTe Growth on GaAs Using Different Etching Techniques

Characterization of CdTe Growth on GaAs Using Different Etching Techniques

Characterization of Smooth CdTe(111) Films by the Conventional Close-Spaced Sublimation Technique

Substrates for the Epitaxial Growth of MCT

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