2016
DOI: 10.1016/j.mee.2015.10.010
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Measurement-based electrical characterization of through silicon vias and transmission lines for 3D integration

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Cited by 21 publications
(4 citation statements)
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“…The via resistance (Rcu_via) and inductance (Lcu_via) computed through (3) and ( 6) are validated with fabrication based experimental results given in [25], [26] as depicted in Fig. 7 It is observed that the via resistance is in well agreement with the experimental result with an average error of 7.35% only.…”
Section: Cnt Based Tsvmentioning
confidence: 52%
“…The via resistance (Rcu_via) and inductance (Lcu_via) computed through (3) and ( 6) are validated with fabrication based experimental results given in [25], [26] as depicted in Fig. 7 It is observed that the via resistance is in well agreement with the experimental result with an average error of 7.35% only.…”
Section: Cnt Based Tsvmentioning
confidence: 52%
“…A test structure for measuring the electrical properties of the via was developed, as shown in figure 6(a) [65,66]. The printed substrate has a rectangular shape with a length of 24 mm and a width of 20 mm.…”
Section: Electrical Properties Of the Via Holementioning
confidence: 99%
“…The pitch between TSVs is also 40 μm, and the insertion loss of single TSV at 20 GHz is about −2.21 dB. The insertion loss of single TSV is much bigger due to the low‐resistivity silicon substrate [17], which means that it is better to adopt the high‐resistivity silicon substrate in the future experiments for the sake of getting a better high frequency electrical performance.…”
Section: Electrical Performance Testmentioning
confidence: 99%