Measurement-to-modeling correlation of the power delivery network impedance of a microprocessor system

Aygün, Kemal; Hill, Michael J.; Ellert, K.D.; Radhakrishnan, Kaladhar

doi:10.1109/epep.2004.1407592

Cited by 8 publications

(16 citation statements)

References 2 publications

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“…6(b) shows that in order to have maximum 200 mV noise, the system, initially, draws about ∼1.1 A on every clock cycle. This can be confirmed from the article [3] written on the plot of current versus time in μs time scale. We also plot possible density distribution of i from their average and standard distribution which is shown in Fig.…”

Section: Data Analysis and Simulation Results For A System Whichsupporting

confidence: 66%

“…We have also investigated other superposition principle techniques and that work is in progress. In [3], one shows the current versus time plot which was calculated from impedance profile measurements and also from the noise measured close to the device. This is what authors in [3] called "reverse engineering" to determine the current drawn by the device.…”

Section: Data Analysis and Simulation Results For A System Whichmentioning

confidence: 99%

“…For this picture, I P (3) is the same as power supply current but I N (3) is the current through the N-channel device. Equation (3) shows that at time t = 0 the current drawn by the device is the highest, V CC /R N , and then the same current decays as a function of time. We will use (3) and the corresponding equivalent circuit, Fig.…”

Section: Theoretical Model To Determine the Current Ramp Of The Dmentioning

confidence: 97%

“…3 can be estimated and measured/simulated for a given package and die. These days the measurements of an impedance profile of the PDN network and the commercially available simulation tools [1]- [3], [7], [9] to calculate impedance profiles from the layout are very accurate. From (3), the current drawn by the device…”

Section: Theoretical Model To Determine the Current Ramp Of The Dmentioning

confidence: 99%

See 3 more Smart Citations

Method to Simulate Rise Time of Current Drawn by a Microprocessor

Bhattacharyya

Baral

2013

IEEE Trans. Compon., Packag. Manufact. Technol.

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We have developed a new method to simulate the effective rise time of current drawn by each cell in a microprocessor so that the total noise is consistent with values measured at the power and ground reference points inside the die. Normally, the measured values are much smaller than simulated values. In this paper, several exponential functions with varying time constants are staggered and combined at different starting time values to generate the effective current profile which was used for noise estimation. The model utilizes a realistic jitterbased distribution function compared to a step function used in existing models for the initial small amount of saturated current ramp. The practical model developed in this paper is useful for optimizing the cost and performance of microprocessors.Index Terms-Average power drawn by CMOS device, current ramp generation, microprocessor currrent simulation, noise simulation, power delivery, power delivery network (PDN), rise time of current, stastical process for power delivery.

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Section: Data Analysis and Simulation Results For A System Whichsupporting

confidence: 66%

Section: Data Analysis and Simulation Results For A System Whichmentioning

confidence: 99%

Section: Theoretical Model To Determine the Current Ramp Of The Dmentioning

confidence: 97%

Section: Theoretical Model To Determine the Current Ramp Of The Dmentioning

confidence: 99%

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Method to Simulate Rise Time of Current Drawn by a Microprocessor

Bhattacharyya

Baral

2013

IEEE Trans. Compon., Packag. Manufact. Technol.

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“…There are two important validation (a) P roc 100 points to observe. First, impedance peaks at around the resonance frequency of 100MHz to 200MHz, which matches a large body of prior work describing typical power delivery network characteristics [1], [2], [8], [24], [25]. Second, the small graph embedded within Fig.…”

Section: A Using Off-the-shelf Componentsmentioning

confidence: 63%

Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling

Reddi

Kanev

Kim

et al. 2010

2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture

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Abstract-Parameter variations have become a dominant challenge in microprocessor design. Voltage variation is especially daunting because it happens so rapidly. We measure and characterize voltage variation in a running Intel R Core TM 2 Duo processor. By sensing on-die voltage as the processor runs singlethreaded, multi-threaded, and multi-program workloads, we determine the average supply voltage swing of the processor to be only 4%, far from the processor's 14% worst-case operating voltage margin. While such large margins guarantee correctness, they penalize performance and power efficiency. We investigate and quantify the benefits of designing a processor for typical-case (rather than worst-case) voltage swings, assuming that a fail-safe mechanism protects it from infrequently occurring large voltage fluctuations. With today's processors, such resilient designs could yield 15% to 20% performance improvements. But we also show that in future systems, these gains could be lost as increasing voltage swings intensify the frequency of fail-safe recoveries. After characterizing microarchitectural activity that leads to voltage swings within multi-core systems, we show that a voltagenoise-aware thread scheduler in software can co-schedule phases of different programs to mitigate error recovery overheads in future resilient processor designs.

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Time‐Domain Analysis

2019

Power Integrity for Electrical and Computer Engineers

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Measurement-to-modeling correlation of the power delivery network impedance of a microprocessor system

Cited by 8 publications

References 2 publications

Method to Simulate Rise Time of Current Drawn by a Microprocessor

Method to Simulate Rise Time of Current Drawn by a Microprocessor

Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling

Time‐Domain Analysis

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