Mechanical and Electrical Analysis of Strained Liner Effect in 35 nm Fully Depleted Silicon-on-Insulator Devices with Ultra Thin Silicon Channels

Abstract

We study the effects of a strained contact etch stop layer (CESL) on fully depleted (FD) silicon-on-insulator (SOI) devices with ultra thin silicon channels. As expected from extensive simulation analysis, the electrical results demonstrate that in spite of the raised source/drain architecture, the stress is effectively transferred from the liner into the underlying channel. Using a tensile liner for the n-type metal-oxide-semiconductor field effect transistor (nMOS) and a compressive liner for the p-type metal-oxide-semiconductor field effect transistor (pMOS), transistor performance enhancements of 10% and 17%, respectively, were obtained. Moreover, with a tensile (/compressive) liner, tensile (/compressive) edge effects become dominant for short devices whereas the stress becomes less tensile (/compressive) for longer devices. Indeed, the balance between these two contributions and the strain level in the channel are highly dependent on geometrical parameters (W, L gate ).

Evaluation of local strain in Si using UV-Raman spectroscopy

“…Therefore SiO 2 is easier to deform than Si. The buried oxide (BOX) in the SOI substrates deformed (compressed in the present case) more than Si; therefore, SOI film on the BOX layer was more strained than that on Cz-Si [38]. We have also verified that thinner SOIs were strained more effectively than thicker ones [39].…”

Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs

“…It can be obtained by the use of strained contact etch stop layers (CESL), which leads to process-induced strain in the channel direction only (or uniaxial) [7]. Also the use of substrate-induced (or biaxial) strained material (or sSOI) is another possible technique to obtain a strained silicon layer by the selective epitaxial growth of Si x Ge 1Àx layers, finally resulting in a top monocrystalline strained silicon layer [8].…”

Analysis of uniaxial and biaxial strain impact on the linearity of fully depleted SOI nMOSFETs

“…The use of uniaxial strain becomes more effective to provide improvements on g m,max for shorter devices as the strain component in direction to the channel becomes more tensile as the gate length is reduced [4]. The major effects due to the stress linear occur at the source/drain regions, which justifies the better results with L reduction [5].…”

“…Strain engineering is necessary to overrule the degradation on the carrier mobility and drive current encountered when scaling the gate stack. Indeed, the improvements provided by the use of strain have been reported for ultrathin body silicon-oninsulator (SOI) devices mainly focusing on the transconductance (and hence the mobility) and the on-state current (I ON ) without degrading the off-state current (I OFF ) leading to a larger I ON /I OFF ratio [3][4][5]. Also the low frequency noise has been demonstrated to be improved by the use of strain [6].…”