Mechanisms of positive gate bias stress induced instabilities in power VDMOSFETs

Stojadinović, N.; Manić, I.; Djorić-Veljković, S.; Davidović, V.; Golubović, S.; Dimitrijev, Sima

doi:10.1016/s0026-2714(01)00143-3

Cited by 36 publications

(42 citation statements)

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“…It lends further support to the hypothesis that the normal degradation occurs by stress-induced defect generation by breaking/distorting of strong Si-Si bonds. Therefore, the carrier trapping mechanism [12], [28], [29] previously proposed to explain the turnaround degradation behavior seems to be not a controlling mechanism in the current observation.…”

Section: Two-stage Degradation Characteristicsmentioning

confidence: 53%

“…Inoue et al [16] showed that a combination of ion contamination effect and SH stress could lead to a similar two-stage degradation. Kouvatsos and Davazoglou [28] observed V th turnaround on solid-phase crystallization poly-Si TFTs stressed by high V g bias with/without a low V d bias and explained the initial V th backshift by hole trapping of preexisting oxide and interface traps via a mechanism of electron tunneling out of neutral oxide traps [29]. In HC degradation, Farmakis et al [12] proposed that hot hole injection followed by hot electron injection can account for such V th turnaround effect.…”

Section: Two-stage Degradation Characteristicsmentioning

confidence: 99%

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Stress Power Dependent Self-Heating Degradation of Metal-Induced Laterally Crystallized n-Type Polycrystalline Silicon Thin-Film Transistors

Wang

Yang

et al. 2007

IEEE Trans. Electron Devices

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Abstract-Self-heating degradation of n-type metal-induced laterally crystallized polycrystalline silicon thin-film transistors is systematically investigated under various stress powers. A two-stage degradation behavior with turnaround effect at the initial stage is characterized. The initial degradation stage is related to breaking of weak Si-H bonds. The floating-body effect by released hydrogen ions is responsible for the observed backshift of the transfer curve during the initial stress. On the other hand, the normal degradation stage occurs by breaking of strong Si-Si bonds and trap generation at grain boundaries (GBs) and the gate oxide/channel interface. Our model is supported by observed different activation energies related to two degradation stages and a direct observation of the continuous increase in GB trap density during the normal degradation. Furthermore, during the normal degradation stage, an anomalous continuous field-effect mobility increase along with its V g dependence shift is first observed. It is clarified that this behavior is not a true channel mobility increase, but a consequence of stress-related trap generation.Index Terms-Field-effect mobility, metal-induced lateral crystallization, polycrystalline silicon (poly-Si), self-heating (SH) degradation, thin-film transistors (TFTs).

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Section: Two-stage Degradation Characteristicsmentioning

confidence: 53%

Section: Two-stage Degradation Characteristicsmentioning

confidence: 99%

Stress Power Dependent Self-Heating Degradation of Metal-Induced Laterally Crystallized n-Type Polycrystalline Silicon Thin-Film Transistors

Wang

Yang

et al. 2007

IEEE Trans. Electron Devices

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“…Others used the test result from a high field stress as a screening method for devices which are to be operated in a radiation environment (Picard et al, 2000a, b). Stojadinovic et al (2001Stojadinovic et al ( , 2002 reported experimental results and theoretical models of oxide-charge trapping and interface trap generation under a high field stress condition.…”

Section: Introductionmentioning

confidence: 99%

Comparison between positive and negative bias stress on N‐channel VDMOSFET transistors

Abboud

Habch

Cuminal

et al. 2013

International Journal of Structural Integrity

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If you would like to write for this, or any other Emerald publication, then please use our Emerald for Authors service information about how to choose which publication to write for and submission guidelines are available for all. Please visit www.emeraldinsight.com/authors for more information. About Emerald www.emeraldinsight.comEmerald is a global publisher linking research and practice to the benefit of society. The company manages a portfolio of more than 290 journals and over 2,350 books and book series volumes, as well as providing an extensive range of online products and additional customer resources and services.Emerald is both COUNTER 4 and TRANSFER compliant. The organization is a partner of the Committee on Publication Ethics (COPE) and also works with Portico and the LOCKSS initiative for digital archive preservation. AbstractPurpose -The purpose of this paper is to apply a negative gate bias stress in order to study instabilities of threshold voltage in N-channel power vertical double-diffused metal-oxide-semiconductor field effect transistor (VDMOSFET). Variations in gate oxide trapped charge and interface trap densities are also calculated. Design/methodology/approach -A threshold voltage shift is detected; the oxide and interface trap densities were evaluated based on a direct measurement of the gate to source capacitance and conductance. Findings -Results presented show that the threshold voltage is decreasing with stress time, the capacitance and conductance curves are altered by applied stress, also the oxide traps and the interface traps densities are increasing with stress time. Originality/value -The positive bias stress seems to be more destructive in the case of the studied devices.

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“…A complete study of the mechanisms responsible for defect creation in metal-oxide-semiconductor field-effect transistors (MOSFETs) during the high electric field stress (HEFS), (a very important stress type [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17]) has been pursued. The idea is to give a complete analysis of the physicochemical processes in the gate oxide (SiO 2 ) and at the gate oxide/substrate (SiO 2 /Si) interface during HEFS, since it could not been found in the literature.…”

Section: Introductionmentioning

confidence: 99%

Physico-chemical processes in metal–oxide–semiconductor transistors with thick gate oxide during high electric field stress

Ristić

Pejović

Jakšić³

2007

Journal of Non-Crystalline Solids

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Mechanisms of positive gate bias stress induced instabilities in power VDMOSFETs

Cited by 36 publications

References 0 publications

Stress Power Dependent Self-Heating Degradation of Metal-Induced Laterally Crystallized n-Type Polycrystalline Silicon Thin-Film Transistors

Stress Power Dependent Self-Heating Degradation of Metal-Induced Laterally Crystallized n-Type Polycrystalline Silicon Thin-Film Transistors

Comparison between positive and negative bias stress on N‐channel VDMOSFET transistors

Physico-chemical processes in metal–oxide–semiconductor transistors with thick gate oxide during high electric field stress

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