Membrane high voltage devices - a milestone concept in power ICs

Abstract

We report for the first time a novel technology concept in Power ICs. We present detailed experimental data obtained during several years of development and demonstrate the application of the new technology in a range of highly efficient switch mode power supplies (SMPS). This technology is capable of delivering more than 3 times higher current density (30 Ncm'), and two to five times the switching speed (500 MIz for 650V rated devices) of state-ofthe-art power IC technologies such as Junction-Isolation or Silicon-on-Insulator. The new concept is based on merging of the MEMS and CMOS SO1 technologies to increase the

Significant enhancement of breakdown voltage for GaN DHFETs by Si substrate removal

“…5. The enhanced device self -heating effect [16] is attributed to the removed Si substrate below the source-to-drain regions in local Si removal case and the presence of low thermal conducting bonding polymer in the global Si removal case. …”

A dynamic self heating model for power SOI Lateral Insulated Gate Bipolar Transistors

“…The silicon on membrane technology (SOM) reported in [1], as shown in Fig. 1, is one of the most promising approaches to improve the isolation of the LIGBT and concomitantly achieve switching frequencies specific to LDMOS devices rather than bipolar devices.…”

“…5 Internal temperature measurents using embedded diodes Self-heating model results The membrane devices fabricated by Camsemi [1] were measured to verify the model against the experimental data. The on state comparison between the model and the measurements are shown in Fig.…”

A Review of techniques used in Lateral Insulated Gate Bipolar Transistor (LIGBT)

“…Membrane technology with back side etching of the silicon substrate under part of the n-drift region of SOI power devices had been proposed [88] and experimentally reported [89]. As mentioned, most of the time JI LIGBTs were not that successful in ICs due to the poor switching speed and cross-talk with adjacent CMOS blocks via common silicon substrate whereas SOI technology had a number of major drawbacks such as a thicker BOX thickness for effective RESURF.…”