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We report for the first time a novel technology concept in Power ICs. We present detailed experimental data obtained during several years of development and demonstrate the application of the new technology in a range of highly efficient switch mode power supplies (SMPS). This technology is capable of delivering more than 3 times higher current density (30 Ncm'), and two to five times the switching speed (500 MIz for 650V rated devices) of state-ofthe-art power IC technologies such as Junction-Isolation or Silicon-on-Insulator. The new concept is based on merging of the MEMS and CMOS SO1 technologies to increase the

In this paper, we propose the use of a retrograde doping profile for the p-well for ultra-high voltage (>10kV) SiC IGBTs. We show that the retrograde p-well effectively addresses the punch-through issue, whilst offering a robust control over the gate threshold voltage. Both the punch-through elimination and gate threshold voltage control are crucial to high-voltage vertical IGBT architectures and are determined by the limits on the doping concentration and depth a conventional p-well implant can have. Without any punch-through, a 10kV SiC IGBT consisting of retrograde p-well yields gate threshold voltages in the range 6-7V with a gate-oxide thickness of 100nm. Gate oxide thickness is typically restricted to 50-60nm in SiC IGBTs if a conventional pwell with 1×10 17 cm -3 is utilized. We further show that the optimized retrograde p-well offers the most optimum switching performance. We propose that such an effective retrograde p-well, which requires low-energy shallow implants and thus key to minimize processing challenges and device development cost, is highly promising for the ultra-high voltage (>10kV) SiC IGBT technology.

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