Memory Architecture Exploration Framework for Cache Based Embedded SOC

Kumar, T.S. Rajesh; Ravikumar, C.P.; Govindarajan, Raghav

doi:10.1109/vlsi.2008.113

Cited by 7 publications

(3 citation statements)

References 9 publications

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“…QtMips supports layered memory architecture, as Fig. 1 shows [7]. As a user-friendly MIPS simulator, QtMips not only realizes basic functions besides simulation of MIPS32 instruction set, convenient simulation executive control (breakpoints, executive time and multi-steps), decimal and hexadecimal transformation, single-step/multi-steps execution highlighting jump, but also achieves the following functions:…”

Section: System Architecturementioning

confidence: 99%

Design and Implementation of MIPS Simulator Oriented Memory Hierarchy Research

Yao

Zeng

Zhao

2012

AMM

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MIPS processor is widely used in embedded system, whose memory hierarchy has such an important effect on the performance and cost that how to design memory hierarchy rapidly is a key problem. To deal with the MIPS memory hierarchy research, we design a MIPS simulator “QtMips”. It is a GUI, Qt-based simulator for MIPS assembly language, which not only collects and analyzes real-time simulation information, but also supports fast memory configuration setting such as hierarchy setting, allocation setting, etc.

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Section: System Architecturementioning

confidence: 99%

Design and Implementation of MIPS Simulator Oriented Memory Hierarchy Research

Yao

Zeng

Zhao

2012

AMM

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“…The on-chip Memory Architecture Fig.1 shows a simplified on-chip memory architecture in embedded systems, which is based on cache and SPM hybrid architecture [3]. In the current work, we limit our attention to on-chip data memory.…”

Section: Overview and Related Workmentioning

confidence: 99%

Fast, Accurate On-Chip Data Memory Performance Estimation

Yao

Xianbin

2011

2011 14th IEEE International Conference on Computational Science and Engineering

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In order to derive the optimal on-chip memory architecture for a given application, the embedded system designer must spend considerable time evaluating potential memory designs. However, tight time-to-market constraints enforce short design cycle time. In this paper we present an effective method to fast and accurately estimate the on-chip data memory performance which employs SPM and cache hybrid architecture for memory design space exploration. The key point is to estimate the performance of data cache by modeling data cache activity. Our method can be applied to all kinds of cache architecture and can statically categorize data cache misses into cold, conflict, and capacity misses, which can provide useful insights for designers to determine data cache architecture. Our evaluation results show that the proposed method can fast and accurately estimate the on-chip memory performance, thus can speedup design process of the on-chip memory architecture of an embedded system.

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“…Their methodology leverages configurable cache architectures to achieve an energy-and performance-conscious adaptive result by mapping the tasks to separate subsections of the cache.By Ji Gu et al [10] the onchip instruction cache is introduced as a potential power hungry component in embedded systems due to its large chip area and high access-frequency.T.S. Rajesh et al [3] presented a memory architecture exploration framework for SPRAMCache based memory architectures for Real-Time Embedded SOC. Their framework integrates memory exploration, data partitioning between SPRAM and Cache but they used just 3 benchmarks.…”

Section: Introductionmentioning

confidence: 99%

Cache power and performance tradeoffs for embedded applications

Alipour

Salehi

Moshari

2011

2011 IEEE International Conference on Computer Applications and Industrial Electronics (ICCAIE)

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As embedded applications have became more complex, design of embedded processors has created a research area for low power and yet high performance architectures. Power consumption is as important as performance in battery-powered embedded systems and in future, embedded processors are to process more computationintensive applications with limited power budgets. Therefore, power consumption of theses processors will become more critical. According to the high contribution of memory access power in total power consumption of embedded systems, memory architecture of embedded systems strongly influences the system design objectives. Cache memories are usually used to improve the performance and power consumption by bridging the gap between the speed and power consumption of the main memory and CPU, therefore, the system performance and power consumption is severely related to the average memory access time and power consumption which makes the cache architecture as a major concern in designing embedded processors. Therefore, the embedded system designer requires a comprehensive design space exploration for memory architecture. In this paper we explore the design space of cache in embedded processors to find out the cache sizes which have the optimum performance/power consumption in embedded applications.

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Memory Architecture Exploration Framework for Cache Based Embedded SOC

Cited by 7 publications

References 9 publications

Design and Implementation of MIPS Simulator Oriented Memory Hierarchy Research

Design and Implementation of MIPS Simulator Oriented Memory Hierarchy Research

Fast, Accurate On-Chip Data Memory Performance Estimation

Cache power and performance tradeoffs for embedded applications

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