Memory at VLSI Circuits Symposium

Itoh, K.; Kurata, Hiroki; Osada, Kensuke; Sekiguchi, Toshio

doi:10.1109/jssc.2008.917527

Cited by 8 publications

(6 citation statements)

References 102 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Major sources of the array power are the traditional V DD -bit-line (BL) precharging scheme in which many BLs swing at a large voltage of V DD , and the folded-BL arrangement with inherently large BL-capacitance C B that not only increases power dissipation but also degrades speed and read stability of the cell. As for the V DD scaling, many attempts to cope with resultant narrower voltage margin have been made so far [1,2]. They include a column-based dynamic power supply [3,4], in which the cell power supply during write is floating or lower than that during read, a dynamic forwardbody-bias just after read and write operations for fast cellnode recovery [5], a two-step word pulse [6,7] with boosting word voltage during write with the help of a sense amplifier, and a boosted WL-voltage FinFET cell [8].…”

Section: Introductionmentioning

confidence: 99%

0.5-V sub-ns open-BL SRAM array with mid-point-sensing multi-power 5T cell

Itoh

Shaik

Amara

2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

Self Cite

View full text Add to dashboard Cite

To achieve 0.5-V high-speed SRAMs, two proposals are demonstrated. One is a multi-power-supply five-transistor cell (5T cell), combined with a boosted word-line voltage and a mid-point sensing enabled by precharging bit-lines to V DD /2. The other is a partial activation of a multi-divided open-bitline array without significant area penalty. Layout and postlayout simulation with a 28-nm fully-depleted planar-logic SOI MOSFET reveal that a 5T-cell 4-kb array in a 128-kb SRAM core is able to achieve x6 faster and x14 lower power than the counterpart 6T-cell array, suggesting a possibility of a 540-ps cycle time at 0.5 V. Keywords-0.5-V 5T-cell SRAM array, multi-divided open bitlines, boosted word-line, and mid-point sensing.

show abstract

Section: Introductionmentioning

confidence: 99%

0.5-V sub-ns open-BL SRAM array with mid-point-sensing multi-power 5T cell

Itoh

Shaik

Amara

2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

Self Cite

View full text Add to dashboard Cite

show abstract

“…low-voltage, low-power SRAM [16,52,250]. Recent published works in literature have shown that the conventional 6T SRAM suffers a severe stability degradation due to access disturbances at low-power mode [11,16]. Thus, several 8T and lOT Low-power and high-stability have been the main themes of SRAM designs in the last interleaving to achieve soft-error tolerance with conventional Error Correcting…”

Section: Resultsmentioning

confidence: 99%

“…As a consequence, one must use larger-thanminimum-sized transistors in memory cells to enhance their stability [8][9][10]. Despite this enhancement, cell stability still cannot cope with the excessive process variations and hence, more-than-6-T cell designs must be used to separate the read/write ports of the cells, therefore greatly improving their noise margin during read and write operations [11][12]. This trend has extended to 11-T cell design to enhance cell read stability, write margin as well as read reliability [7] at the cost of more than 60% cell area overhead.…”

Section: Motivationmentioning

confidence: 99%

“…Previously, circuit designers have strived for higher speed performance [25]. However, with the explosion of handheld gadgets market and the continuous miniaturization of device feature size, power consumption management has been given the highest priority followed by the system reliability [11]. Nevertheless, these two factors cannot be optimized without jeopardizing each other (at least, there is not yet an obvious solution).…”

Section: Chapter 2 Literature Reviewmentioning

confidence: 99%

“…11 The proposed design coupled with a simplified read-cycle-only memory system.Consider both RS 1 and CS2 being activated during a read operation. The pre-charge signal (PRE) turns N5 and N6 off, allowing the DL voltages to change freely.…”

mentioning

confidence: 99%

See 2 more Smart Citations

Design of low-voltage low-power nano-scale SRAMs

Tuan¹

View full text Add to dashboard Cite

Static Random Access Memory (SRAM)-based cache is one of the most important components of state-of-the-art VLSI systems. It is responsible for increasing the speed of data flows, and hence the speed of the whole electronic system. SRAM is prevalently utilized in the design of modern microprocessors for bridging the widening divergence between the performances of the Central Processing Unit (CPU) and the Dynamic RAM (DRAM)-based main memory. This trend is accentuated by the never-ending market demand for sophisticated communication and multimedia applications, which require high-tech portable electronic gadgets with high-performance as the requisite feature. As the on-chip memory occupies a large portion of the chip area, the power dissipated within the memory, both active and standby, will become a dominant part of the chip's total power consumption. In view of the above, there is invariably an apparent urgency to address these two often-conflicting power and performance requirements. Our research focuses on SRAM cell design for ultra low-voltage ultra low-power applications. Two SRAM cell topologies have been proposed with an improved noise margin and hence can operate at very low supply voltages to save power. Our first proposal is a 10T SRAM cell design that has 4x read and lox leakage power reduction when compared to the conventional 6T design. The proposed cell has separate readwrite ports and hence its read noise margin is 31% higher than that of the conventional 6T design. We also proposed a special read scheme that accesses only one cell during read out and hence more than 98% of cell active current is saved (assuming that each row has 128 cells and operating frequency is 250 MHz). This hefty amount of power reduction is obtained at the cost of 33% cell area overhead and 23% of write-ability. Extensive simulations on two SRAM macros using a standard 65nm / 1V CMOS process showed that the total read power consumption of the proposed design has reduced to 25% of that of the conventional 6T design. It also has smaller write power consumption. More

show abstract

Design and array implementation a cantilever-based non-volatile memory utilizing vibrational reset

Tuan

Gopal

Singh

et al. 2013

2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)

View full text Add to dashboard Cite

This paper proposes a cantilever-based memory structure for storing binary data at extreme operating temperature (up to 300 C) in rugged electronics. The memory bit (0/1) is formed by opening/closing of an electrostatic switch. Permanent retention is obtained by adhesive force between two smooth surfaces in contact, eliminating leakage observed in all types of storage-layer-based NVMs. The Reset utilizes a train of short pulses to break the adhesion between the electrodes. This allows the Nano-electromechanical switch (NEMS) memory to be implemented using a simple bi-layer design and easily integrated with CMOS platforms. We propose an array structure where each memory cell consists of a NEMS memory device and one NMOS transistor for full random-access operation.

show abstract

Memory at VLSI Circuits Symposium

Cited by 8 publications

References 102 publications

0.5-V sub-ns open-BL SRAM array with mid-point-sensing multi-power 5T cell

0.5-V sub-ns open-BL SRAM array with mid-point-sensing multi-power 5T cell

Design of low-voltage low-power nano-scale SRAMs

Design and array implementation a cantilever-based non-volatile memory utilizing vibrational reset

Contact Info

Product

Resources

About