Memory Conflict Analysis and Implementation of a Re-configurable Interleaver Architecture Supporting Unified Parallel Turbo Decoding

Asghar, Rizwan; Wu, Di; Eilert, Johan; Liu, Dake

doi:10.1007/s11265-009-0394-8

Cited by 22 publications

(13 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The interleaver structure in the current and previous 3G standards do not have a parallel structure which makes it difficult to realize the parallelization of the MAP decoders. Expensive write buffers have to be used to reduce the memory collision caused by the interleaver [9,48]. However, when the parallelism degree increases, the collisions cannot be effectively resolved by using write buffers.…”

Section: Parallel Turbo Decoder Architecturementioning

confidence: 99%

Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder

Sun

Cavallaro

2011

Integration

View full text Add to dashboard Cite

a b s t r a c tWe present an efficient VLSI architecture for 3GPP LTE/LTE-Advance Turbo decoder by utilizing the algebraic-geometric properties of the quadratic permutation polynomial (QPP) interleaver. The highthroughput 3GPP LTE/LTE-Advance Turbo codes require a highly-parallel decoder architecture. Turbo interleaver is known to be the main obstacle to the decoder parallelism due to the collisions it introduces in accesses to memory. The QPP interleaver solves the memory contention issues when several MAP decoders are used in parallel to improve Turbo decoding throughput. In this paper, we propose a low-complexity QPP interleaving address generator and a multi-bank memory architecture to enable parallel Turbo decoding. Design trade-offs in terms of area and throughput efficiency are explored to find the optimal architecture. The proposed parallel Turbo decoder has been synthesized, placed and routed in a 65-nm CMOS technology with a core area of 8.3 mm 2 and a maximum clock frequency of 400 MHz. This parallel decoder, comprising 64 MAP decoder cores, can achieve a maximum decoding throughput of 1.28 Gbps at 6 iterations &

show abstract

Section: Parallel Turbo Decoder Architecturementioning

confidence: 99%

Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder

Sun

Cavallaro

2011

Integration

View full text Add to dashboard Cite

show abstract

“…In [12] and [13], the authors introduced misalignment among memory access paths using delay line buffers. They also use FIFOs to buffer LLRs when memory conflicts occur.…”

Section: Related Workmentioning

confidence: 99%

“…The solution in [23] uses large amounts of buffers. The authors in [12] and [13] only show the results for parallelism of 4. In addition, the interleaver in [12] uses a large number of memory banks (24 sub-banks) which is quite inefficient.…”

Section: E Architecture Comparison With Related Workmentioning

confidence: 99%

High-throughput Contention-Free concurrent interleaver architecture for multi-standard turbo decoder

Wang

Sun

Cavallaro

et al. 2011

ASAP 2011 - 22nd IEEE International Conference on Application-Specific Systems, Architectures and Processors

View full text Add to dashboard Cite

Abstract-To meet the higher data rate requirement of emerging wireless communication technology, numerous parallel turbo decoder architectures have been developed. However, the interleaver has become a major bottleneck that limits the achievable throughput in the parallel decoders due to the massive memory conflicts. In this paper, we propose a flexible Double-Buffer based Contention-Free (DBCF) interleaver architecture that can efficiently solve the memory conflict problem for parallel turbo decoders with very high parallelism. The proposed DBCF architecture enables high throughput concurrent interleaving for multi-standard turbo decoders that support UMTS/HSPA+, LTE and WiMAX, with small datapath delays and low hardware cost. We implemented the DBCF interleaver with a 65nm CMOS technology. The implementation of this highly efficient DBCF interleaver architecture shows significant improvement in terms of the maximum throughput and occupied chip area compared to the previous work.

show abstract

“…Some of these designs targeted very low-cost solutions. A recent work in [18] provides a good unified design for different standards; however, it covers only the turbo code interleavers and does not meet the complete baseband processing requirements demanding an all-in-one solution. The work in [19][20][21][22] covers the DVB-related interleaver implementations.…”

Section: Previous Workmentioning

confidence: 99%

“…As the rotation is fixed for a specific spatial stream, thus the starting value r ks = (−J ROT )%N also holds for all run time computations. Equation (18) in combination with (10) can be written as…”

Section: Frequency Interleaving In 802mentioning

confidence: 99%

Multimode Flex-Interleaver Core for Baseband Processor Platform

Asghar

Liu

2010

Journal of Computer Systems, Networks, and Communications

Self Cite

View full text Add to dashboard Cite

This paper presents a flexible interleaver architecture supporting multiple standards like WLAN, WiMAX, HSPA+, 3GPP-LTE, and DVB. Algorithmic level optimizations like 2D transformation and realization of recursive computation are applied, which appear to be the key to reach to an efficient hardware multiplexing among different interleaver implementations. The presented hardware enables the mapping of vital types of interleavers including multiple block interleavers and convolutional interleaver onto a single architecture. By exploiting the hardware reuse methodology the silicon cost is reduced, and it consumes 0.126 mm 2 area in total in 65 nm CMOS process for a fully reconfigurable architecture. It can operate at a frequency of 166 MHz, providing a maximum throughput up to 664 Mbps for a multistream system and 166 Mbps for single stream communication systems, respectively. One of the vital requirements for multimode operation is the fast switching between different standards, which is supported by this hardware with minimal cycle cost overheads. Maximum flexibility and fast switchability among multiple standards during run time makes the proposed architecture a right choice for the radio baseband processing platform.

show abstract

Memory Conflict Analysis and Implementation of a Re-configurable Interleaver Architecture Supporting Unified Parallel Turbo Decoding

Cited by 22 publications

References 13 publications

Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder

Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder

High-throughput Contention-Free concurrent interleaver architecture for multi-standard turbo decoder

Multimode Flex-Interleaver Core for Baseband Processor Platform

Contact Info

Product

Resources

About