Memory-Link Compression Schemes: A Value Locality Perspective

Thuresson, Martin; Spracklen, Lawrence; Stenström, Per

doi:10.1109/tc.2008.28

Cited by 45 publications

(36 citation statements)

References 28 publications

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“…Before the study of data compression on NoCs was carried out, there were already many efforts of applying data compression on bus and cache [6], [7], [8], [9]. Moreover, a study carried out in Ref.…”

Section: Related Workmentioning

confidence: 99%

Adaptive Data Compression on 3D Network-on-Chips

Matsutani

Sekiya

et al. 2012

IPSJ Online Transactions

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Abstract:The three-dimensional Network-on-Chip (3D NoC) is an emerging research topic exploring the network architecture of 3D ICs that stack several wafers or dies. As such topics being extensively studied, it is found negative impacts of 3D NoC's vertical interconnects are raising concerns considering their footprint sizes and routability degradation. In our evaluation, we found such vertical bandwidth limitation can dramatically degrade system performance by up to 2.3×. Since such limitations come from physical design constraints, to mitigate performance degradation, we have no other choice but to reduce the amount of communication data on-chip, especially for those data moving vertically. In this paper, therefore, we carry out a study of data compression on 3D NoC architectures with a comprehensive set of scientific workloads. Firstly, we propose an adaptive data compression scheme for 3D NoCs, taking account of the vertical bandwidth limitation and data compressibility. Secondly, we evaluate our proposal on a 3D NoC platform and we observe that the compressibility based adaptive compression is very useful against incompressible data while the location-based adaptive compression is more effective with more layers for the 3D NoC. Thirdly, we find that in a bandwidth limited situation like a CMP with 3D NoCs having multiple connected layers, adaptive data compression with location-based control or with both compressibility and location based control is very promising if the number of layers grows.

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Section: Related Workmentioning

confidence: 99%

Adaptive Data Compression on 3D Network-on-Chips

Matsutani

Sekiya

et al. 2012

IPSJ Online Transactions

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“…It can be used to improve both capacity (e.g., of caches, DRAM, non-volatile memories [27], [2], [7], [18], [4], [17], [22], [16], [26]) and bandwidth utilization (e.g., of on-chip and off-chip interconnects [8], [3], [24], [21], [17], [22], [26]). Several recent works focus on bandwidth compression to decrease memory traffic by transmitting data in a compressed form in both CPUs [17], [24], [3] and GPUs [21], [17], [26], which results in better system performance and energy consumption. Bandwidth compression proves to be particularly effective in GPUs because GPUs are often bottlenecked by memory bandwidth [15], [14], [13], [28], [26].…”

Section: Introductionmentioning

confidence: 99%

Toggle-Aware Compression for GPUs

Pekhimenko

Bolotin

O’Connor

et al. 2015

IEEE Comput. Arch. Lett.

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Abstract-Memory bandwidth compression can be an effective way to achieve higher system performance and energy efficiency in modern data-intensive applications by exploiting redundancy in data. Prior works studied various data compression techniques to improve both capacity (e.g., of caches and main memory) and bandwidth utilization (e.g., of the on-chip and off-chip interconnects). These works addressed two common shortcomings of compression: (i) compression/decompression overhead in terms of latency, energy, and area, and (ii) hardware complexity to support variable data size. In this paper, we make the new observation that there is another important problem related to data compression in the context of the communication energy efficiency: transferring compressed data leads to a substantial increase in the number of bit toggles (communication channel switchings from 0 to 1 or from 1 to 0). This, in turn, increases the dynamic energy consumed by on-chip and off-chip buses due to more frequent charging and discharging of the wires. Our results, for example, show that the bit toggle count increases by an average of 2.2× with some compression algorithms across 54 mobile GPU applications. We characterize and demonstrate this new problem across a wide variety of 221 GPU applications and six different compression algorithms. To mitigate the problem, we propose two new toggle-aware compression techniques: Energy Control and Metadata Consolidation. These techniques greatly reduce the bit toggle count impact of the six data compression algorithms we examine, while keeping most of their bandwidth reduction benefits.

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“…Bus compression: Bus compression can increase the bandwidth of a narrow bus for wide data [17], [18]. Bus-Expander stores the repeated high order bits of data into a table [17].…”

Section: Related Workmentioning

confidence: 99%

“…Cache compression increases the cache capacity by compressing block data and accommodating more blocks in a fixed space [15], [16]. Bus compression also expands the bus width by encoding a wide data as a small size code [17], [18]. Recently data compression is explored in the on-chip network domain for performance and power [4].…”

Section: Introductionmentioning

confidence: 99%