Memory-memory-memory Clos-network packet switches with in-sequence service

Dong, Ziqian; Rojas‐Cessa, Roberto; Oki, Eiji

doi:10.1109/hpsr.2011.5986014

Cited by 14 publications

(34 citation statements)

References 17 publications

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“…Last, there are k output modules at the third stage, each of size m×n. Extensive work has been done on Clos-network switches in all their variants such as S 3 [6], MSM [8] [11], SMM [9] and MMM [7] [2]. Unfortunately, none of the existing Clos-switching architectures has been shown to provide scalability in terms of cost, performance and hardware complexity.…”

Section: Related Workmentioning

confidence: 99%

“…The MSM architecture requires expensive and complex input modules. Each of these input modules is required to cater for a high number of separate FIFO queues (n.k) in order to avoid the HoL blocking [7] [18]. Additionally, each of these queues is required to run (n+1) times the line rate [10].…”

Section: Related Workmentioning

confidence: 99%

“…Despite their scalability potential, almost all existing Clos network based proposals are either too complex to be implemented, exhibit prohibitively high cost or have low performance. The input queuing structure at the input modules (IMs) is generally complex, requiring excessive number of queues to avoid the Head-of-Line (HoL) blocking [8] [7]. In addition to their impact on the scheduling complexity, these queues are generally required to be of output queued type and run much faster than the external input line rate.…”

Section: Introductionmentioning

confidence: 99%

“…As in single-stage, buffer placement defines the type of the multistage Clos switch. According to the stage where buffers are inserted, a Clos network could be a Space-Space-Space (S 3 ) [6] network without buffers or Memory-Memory-Memory (MMM) [7] with buffered switching units in all stages. Other combinations have also been studied [8] [9].…”

Section: Introductionmentioning

confidence: 99%

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A Multi-Stage Packet-Switch Based on NoC Fabrics for Data Center Networks

Hassen

Mhamdi

2015

2015 IEEE Globecom Workshops (GC Wkshps)

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Abstract-Bandwidth-hungry applications such as Cloud computing, video sharing and social networking drive the creation of more powerful Data Centers (DCs) to manage the large amount of packetized traffic. Data center network (DCN) topologies rely on thousands of servers that exchange data via the switching backbone. Cluster switches and routers are employed to provide interconnectivity between elements of the same DC and inter DCs and must be able to handle the continuously variable loads. Hence, robust and scalable switching modules are needed. Conventional DCN switches adopt crossbars or/and blocks of memories in multistage interconnection architectures (commonly 2-Tiers or 3-Tiers). However, current multistage packet switch architectures, with their space-memory variants, are either too complex to implement, have poor performance, or not cost effective. In this paper, we propose a novel and highly scalable multistage packet-switch design based on Networks-on-Chip (NoC) fabrics for DCNs. In particular, we describe a novel three-stage packet-switch fabric with a Round-Robin packets dispatching scheme where each central stage module is based on a Unidirectional NoC (UDN), instead of a conventional singlehop crossbar fabric. The proposed design, referred to as Clos-UDN, overcomes all the shortcomings of conventional multistage architectures. In particular, as we shall demonstrate, the proposed Clos-UDN architecture: (i) Obviates the need for a complex and costly input modules, by means of few, yet simple, input FIFO queues. (ii) Avoids the need for a complex and synchronized scheduling process over a high number of input-output modules and/or port pairs. (iii) Provides speedup, load balancing and path-diversity thanks to a dynamic dispatching scheme as well as the NoC based fabric nature. Extensive simulation studies are conducted to compare the proposed Clos-UDN switch to conventional multistage switches. Simulation results show that the Clos-UDN outperforms conventional design under a wide range of input traffic scenarios, making it highly appealing for ultra-high capacity DC networks.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Multi-Stage Packet-Switch Based on NoC Fabrics for Data Center Networks

Hassen

Mhamdi

2015

2015 IEEE Globecom Workshops (GC Wkshps)

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“…This problem may be alleviated in the future by CQ switches, where it is possible to organize VOQs or VOMQs in cross-point buffers. These kinds of chips are not on the market yet, but the switches are considered in [15,16]. Currently, the speed up problem may The MCNS allows one cell to be sent from each IM to any OM using a direct link, and no arbitration process is needed.…”

Section: The Modified Msm Clos-network Switch (Mcns)mentioning

confidence: 99%

Packet dispatching using module matching in the modified MSM Clos-network switch

Kleban

2017

Telecommun Syst

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A modified memory-space-memory (MSM) Closnetwork switch, called MCNS, with a module-level matching packet dispatching scheme, is presented in the paper. The MCNS is a modification of the MSM Clos-network switch proposed to simplify the packet dispatching scheme. In this paper, we evaluate the combinatorial properties of the MCNS, as well as a new module-level matching packet dispatching algorithm. We also show how this algorithm can be implemented in an field-programmable gate array chip. Selected simulation results obtained for the MCNS are compared with the results obtained for the MSM Clos-network switch using other module-level matching algorithms.

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