Memory module-level testing and error behaviors for phase change memory

Zhang, Zhe; Xiao, Weijun; Park, Noh-Hyun; Lilja, David J.

doi:10.1109/iccd.2012.6378664

Cited by 17 publications

(16 citation statements)

References 13 publications

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“…State‐of‐the‐art PCM testing methodology are mainly based on March tests . Two methodologies can be identified: (1) testing based on conventional March test algorithm and (2) testing based on a modified March test (ie, March‐PCM) . Both methodologies have been shown to correctly detect the PCM specific faults.…”

Section: Testing Methodologiesmentioning

confidence: 99%

“…The conventional March algorithm proposed for PCM memory test consists of 6 March steps . Each step is applied to memory cells from first address in the memory block up to the last address (↑ increasing addressing order).…”

Section: Testing Methodologiesmentioning

confidence: 99%

“…Step 6: performing another read operation (expecting “1”), M 6 : (r 1 ). It has been shown that this March algorithm can detect any type of PCM fault inside the memory . The resulting March algorithm is

March = ({};;;;;, true↑ ((),,, {normalw}_{0}, {normalr}_{0}, {normalr}_{0}), true↑ ((), {normalr}_{0}), true↑ ((), {normalr}_{0}), true↑ ((),,, {normalw}_{1}, {normalr}_{1}, {normalr}_{1}), true↑ ((), {normalr}_{1}), true↑ ((), {normalr}_{1})) .

…”

Section: Testing Methodologiesmentioning

confidence: 99%

“…This is the most common and relevant permanent fault in PCM devices. It is also called Stuck at Reset (SR) [39]. This fault occurs due to cell's over cycling, which can cause the chalcogenide material to get loosen from its top electrode and become separated from it.…”

Section: Sa0mentioning

confidence: 99%

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State of the art and challenges for test and reliability of emerging nonvolatile resistive memories

Vatajelu

Pouyan

Hamdioui

2017

Circuit Theory & Apps

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Summary The power and reliability issues of today's memories (static and dynamic RAMs) reduce the advances achieved by their implementation in scaled technology. There are several emergent memory technologies that address the technical constraints of today's memories, among which the most promising solutions are the resistance‐based memories, such as phase change memories, the redox‐based resistive memories, and the spin‐transfer torque magnetic memories. These technologies are facing various challenges that have to be addressed to render them efficient in today's applications. Until recently, research focus was on the design for performance and power efficiency, but lately, the test and reliability issues of these devices have become of major concern to the community. This paper presents an overview of the challenges and proposed test and reliability boost solutions developed to suit the needs of the emerging memories under analysis. It underlines (1) the unique faults that occur in the memory cell due to known issues in the emerging storage devices, (2) the dedicated solutions developed for efficient testing of the emerging memories under study, (3) the main reliability concerns related to the emerging storage devices, and (4) the design solutions targeted at mitigating these reliability issues. Copyright © 2017 John Wiley & Sons, Ltd.

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Section: Testing Methodologiesmentioning

confidence: 99%

Section: Testing Methodologiesmentioning

confidence: 99%

March = ({};;;;;, true↑ ((),,, {normalw}_{0}, {normalr}_{0}, {normalr}_{0}), true↑ ((), {normalr}_{0}), true↑ ((), {normalr}_{0}), true↑ ((),,, {normalw}_{1}, {normalr}_{1}, {normalr}_{1}), true↑ ((), {normalr}_{1}), true↑ ((), {normalr}_{1})) .

…”

Section: Testing Methodologiesmentioning

confidence: 99%

Section: Sa0mentioning

confidence: 99%

See 2 more Smart Citations

State of the art and challenges for test and reliability of emerging nonvolatile resistive memories

Vatajelu

Pouyan

Hamdioui

2017

Circuit Theory & Apps

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“…Zhang et al [17] conducted a study on a real PCM chip to categorize the type of errors that could occur when programming PCM cells. The study revealed that the error rate of hard errors (stuck-at faults) is at least ten order of magnitudes higher than that of soft errors which renders transient errors negligible in the context PCM chips.…”

Section: Introductionmentioning

confidence: 99%

Symbol Shifting: Tolerating More Faults in PCM Blocks

Maddah

Cho

Melhem

2016

IEEE Trans. Comput.

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Phase-change memory (PCM) has emerged as a candidate that overcomes the physical limitations faced by DRAM and NAND flash memory. While PCM has desirable properties in terms of scalability and density, it suffers from limited endurance. Repeated writes cause PCM cells to wear out and get permanently stuck at a specific value. Recovering from stuck-at faults through a proactive error correcting scheme is essential for the widespread adoption of PCM.In this paper, we propose Symbol Shifting as a practical technique to increase the number of faults that an error correcting code can cover in single and multilevel cells memory chips. Since stuck-at cells can still be read, errors are manifested only when a worn-out cell is to be programmed with a symbol value different than the value it is stuck at. After a write operation fails for a given block of data, another write operation is attempted with all original data symbols shifted to another memory level. Shifting the data is likely to bring the number of errors within the nominal capability of the deployed error correcting code. Requiring only one additional auxiliary cell, Symbol Shifting can increase the number of faults that an error correcting code can cover by up to double the nominal capability and extends the lifetime by up to 37%.

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