Memory system characterization of commercial workloads

Barroso, Luiz André; Gharachorloo, Kourosh; Bugnion, Edouard

doi:10.1109/isca.1998.694758

Cited by 161 publications

(146 citation statements)

References 19 publications

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“…For instance, the workload characterization studies that analyze micro-architectural behavior of the OLTP workloads demonstrate that transactions exhibit significant stalls during execution [2,7,22,62]; a result we corroborate in Section 6.2. It has also been shown that sharedeverything systems have frequent shared read-write accesses [9,22], which are difficult to predict [56].…”

Section: Shared-everything Database Deploymentssupporting

confidence: 68%

“…The absolute difference in performance is much lower than in the case of counter incrementing because executing a transaction has significant start-up and finish costs, and during transaction execution a large fraction of the time is spent on operations other than accessing data. For instance, studies show that around 20% of the total instructions executed during OLTP are data loads or stores (e.g., [7,22]). …”

Section: Variable Communication Latenciesmentioning

confidence: 99%

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Characterization of the Impact of Hardware Islands on OLTP

Porobic

Pandis

Branco³

et al. 2015

The VLDB Journal

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Modern hardware is abundantly parallel and increasingly heterogeneous. The numerous processing cores have non-uniform access latencies to the main memory and processor caches, which causes variability in the communication costs. Unfortunately, database systems mostly assume that all processing cores are the same and that microarchitecture differences are not significant enough to appear in critical database execution paths. As we demonstrate in this paper, however, non-uniform core topology does appear in the critical path and conventional database architectures achieve suboptimal and even worse, unpredictable performance. We perform a detailed performance analysis of OLTP deployments in servers with multiple cores per CPU (multicore) and multiple CPUs per server (multisocket). We compare different database deployment strategies where we vary the number and size of independent database instances running on a single server, from a single shared-everything instance to fine-grained shared-nothing configurations. We quantify the impact of non-uniform hardware on various deployments by (a) examining how efficiently each deployment uses the available hardware resources and (b) measuring the impact of distributed transactions and skewed requests on different workloads. We show that no strategy is optimal for all cases and that the best choice depends on the combination of hardware topology and workload characteristics. Finally, we argue that transaction processing systems must be aware of the hardware topology in order to achieve predictably high performance.

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Section: Shared-everything Database Deploymentssupporting

confidence: 68%

Section: Variable Communication Latenciesmentioning

confidence: 99%

Characterization of the Impact of Hardware Islands on OLTP

Porobic

Pandis

Branco³

et al. 2015

The VLDB Journal

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“…Despite an abundance of research over the years, instruction cache (icache) miss stalls remain a source of performance degradation for many commercial applications [2] [7][10] [11] [15][17] [23]. Due to the relatively larger performance cost of data cache misses in most applications, research and development has focused primarily on the data cache miss problem instead.…”

Section: Introductionmentioning

confidence: 99%

Call-chain Software Instruction Prefetching in J2EE Server Applications

Nagpurkar¹,

Cain²,

Serrano³

et al. 2007

16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007)

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We present a detailed characterization of instruction cache performance for IBM's J2EE-enabled web server, WebSphere Application Server (WAS). When running two J2EE benchmarks on WebSphere, we find that instruction cache misses cause a 12% performance penalty on currentgeneration Power5-based multiprocessor systems. To mitigate this performance loss, we describe a new call-chain based algorithm for inserting software prefetch instructions, and evaluate its potential for improved instruction cache performance. The performance of this algorithm depends on the selection of several independent parameters which control the distance and number of prefetches inserted for a particular method. We select these parameters through characterization of the WebSphere applications, and ultimately find that our call-chain based insertion algorithm achieves significant reduction in instruction cache miss rate for Java methods.

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“…More specifically, Keeton et al measure an instruction-related stall component of 41% of the total execution time for Informix running TPC-C on a PentiumPro [KP+98]. When running transactional (TPC-B and TPC-C) and decisionsupport (TPC-H) benchmarks on top of Oracle on Alpha processors, instruction stalls account for 45% and 30% of the execution time, respectively [BGB98] [SBG02]. A recent study of DB2 7.2 running TPC-C on Pentium III [SA04] attributes 22% of the execution time to instruction stalls.…”

Section: Database Workloads On Modern Processorsmentioning

confidence: 99%

STEPS Towards Cache-Resident Transaction Processing

Harizopoulos

Ailamaki

2004

Proceedings 2004 VLDB Conference

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Online transaction processing (OLTP) is a multibillion dollar industry with high-end database servers employing state-of-the-art processors to maximize performance. Unfortunately, recent studies show that CPUs are far from realizing their maximum intended throughput because of delays in the processor caches. When running OLTP, instruction-related delays in the memory subsystem account for 25 to 40% of the total execution time. In contrast to data, instruction misses cannot be overlapped with out-of-order execution, and instruction caches cannot grow as the slower access time directly affects the processor speed. The challenge is to alleviate the instructionrelated delays without increasing the cache size.We propose Steps, a technique that minimizes instruction cache misses in OLTP workloads by multiplexing concurrent transactions and exploiting common code paths. One transaction paves the cache with instructions, while close followers enjoy a nearly miss-free execution. Steps yields up to 96.7% reduction in instruction cache misses for each additional concurrent transaction, and at the same time eliminates up to 64% of mispredicted branches by loading a repeating execution pattern into the CPU. This paper (a) describes the design and implementation of Steps, (b) analyzes Steps using microbenchmarks, and (c) shows Steps performance when running TPC-C on top of the Shore storage manager. PrologueIn the past decade, research has proposed techniques to identify and reduce CPU performance bottlenecks in database workloads. As memory access times improve much slower than processor speed, performance is bound by instruction and data cache misses that cause expensive main-memory accesses. Research [AD+99][LB+98] [SBG02] shows that decision-support (DSS) applications are predominantly delayed by data cache misses, whereas OLTP is bounded by instruction cache misses. Although several techniques can reduce data cache misses (larger caches, out-of-order execution, better data placement), none of these can effectively address instruction caches.

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Memory system characterization of commercial workloads

Cited by 161 publications

References 19 publications

Characterization of the Impact of Hardware Islands on OLTP

Characterization of the Impact of Hardware Islands on OLTP

Call-chain Software Instruction Prefetching in J2EE Server Applications

STEPS Towards Cache-Resident Transaction Processing

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