Memory Window and Endurance Improvement of Hf0.5Zr0.5O2-Based FeFETs with ZrO2 Seed Layers Characterized by Fast Voltage Pulse Measurements

Abstract

The HfO 2 -based ferroelectric field effect transistor (FeFET) with a metal/ferroelectric/insulator/semiconductor (MFIS) gate stack is currently being considered as a possible candidate for high-density and fast write speed non-volatile memory. Although the retention performance of the HfO 2 -based FeFET with a MFIS gate stack could satisfy the requirements for practical applications, its memory window (MW) and reliability with respect to endurance should be further improved. This work investigates the advantage of employing ZrO 2 seed layers on the MW, retention, and endurance of the Hf 0.5 Zr 0.5 O 2 (HZO)-based FeFETs with MFIS gate stacks, by using fast voltage pulse measurements. It is found that the HZO-based FeFET with a ZrO 2 seed layer shows a larger initial and 10-year extrapolated MW, as well as improved endurance performance compared with the HZO-based FeFET without the ZrO 2 seed layer. The results indicate that employing of a direct crystalline high-k/Si gate stack would further improve the MW and reliability of the HfO 2 -based FeFETs.

Hafnium–zirconium oxide interface models with a semiconductor and metal for ferroelectric devices

“…In contrast, a direct interface between HZO and metal electrode can be relatively easily achieved by suppressing the interlayer DE formation. This finding is consistent with MIM capacitors showing better endurance of 10 11 cycles10,11 than MIS Si FeFETs (10 7 cycles[7][8][9] ). By controlling the DE interlayer at metal-HZO, it would be possible to further improve the endurance of MIM devices.ConclusionsAtomic stack models are developed to elucidate the atomic scale behaviour of semiconductor-HZO and metal-HZO interfaces with detailed atomic and electronic structure information, and the findings from DFT modeling provide an insight on the origins of different endurance behaviour of HZObased FE devices with MIM and MIS structures.…”

“…Current FeFETs, in metal-insulator-semiconductor (MIS) geometry with HZO as the insulator, typically have endurance less than 10 7 cycles for silicon-based devices. [7][8][9] In contrast, current HZO-based metal-insulator-metal (MIM) capacitors can have endurances as high as 10 11 cycles. 10,11 While the main difference is the underlying substrate on which HZO is grown (i.e., semiconductor for MIS, and metal for MIM), the detailed nature of the semiconductor-HZO and metal-HZO interfaces are not known with fundamental understanding at the atomic scale.…”

“…It is known that the loss of ferroelectricity of HZO films is correlated with accumulation of defects (e.g., interface trap states with Dit) as a result of repeated polarization switching. 7 It is also known that DE interlayers are formed at the interfaces (semiconductor-HZO and metal-HZO) during the device fabrication, and that the interlayers at semiconductor-HZO interfaces may help reduce defect formation and increase endurance in MIS devices. 7 However, it is not clearly understood how the interlayers improve the semiconductor-HZO interface with the reduced Dit and enhanced endurance nor how to optimize the interlayers for improved endurance when the thicknesses of the ferroelectric and interlayers are scaled.…”

High‐Performance and High‐Endurance HfO2‐Based Ferroelectric Field‐Effect Transistor Memory with a Spherical Recess Channel

“…[21][22][23][24] A majority of the recent studies on HfO 2 -FeFETs have focused on increasing the capacitance of the interfacial layer (such as by replacing it with a high-k material or a significantly thin (≈1 nm) oxide layer) to improve endurance. [25][26][27] In addition, efforts devoted toward the development of HfO 2 ferroelectrics have primarily focused on increasing P s , which is used for sensing margins in MFM capacitors. [28][29][30][31][32][33][34][35] In this study, the influence of switching polarization (P s ) on the charge injection/trapping has been studied, and we proposed a novel structure of FeFET to reduce the electric field through dielectric (E DE ).…”

The Impact of Contact Position on the Retention Performance in Thin‐Film Ferroelectric Transistors

“…Ferroelectric memory, typically realized using the ferroelectric thin-film transistor (FeTFT), has progressed toward high endurance, [1,2] multilevel storage, [3][4][5] and flexible device fabrication. [6,7] The application of 2D materials, such as black phosphorus, MoS 2 , and graphene, provides more choice for tunable direct bandgap and high carrier mobility semiconductors.…”