Memristor-based memory: The sneak paths problem and solutions

Zidan, Mohammed A.; Fahmy, Hossam A. H.; Hussain, Muhammad Mustafa; Salama, Khaled N.

doi:10.1016/j.mejo.2012.10.001

Cited by 381 publications

(200 citation statements)

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“…On physical device side, a memristor passive crossbar architecture generally suffers from sneak paths (undesired paths parallel to the intended path for current sensing) [18], [65], [72]- [74]. The sneak-paths problem is caused by directly connecting resistive-type cells on sensing grid to the high-impedance terminations of the unselected lines.…”

Section: Discussionmentioning

confidence: 99%

Homogeneous Spiking Neuromorphic System for Real-World Pattern Recognition

Saxena

Zhu

2015

IEEE J. Emerg. Sel. Topics Circuits Syst.

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Abstract-A neuromorphic chip that combines CMOS analog spiking neurons and memristive synapses offers a promising solution to brain-inspired computing, as it can provide massive neural network parallelism and density. Previous hybrid analog CMOS-memristor approaches required extensive CMOS circuitry for training, and thus eliminated most of the density advantages gained by the adoption of memristor synapses. Further, they used different waveforms for pre and post-synaptic spikes that added undesirable circuit overhead. Here we describe a hardware architecture that can feature a large number of memristor synapses to learn real-world patterns. We present a versatile CMOS neuron that combines integrate-and-fire behavior, drives passive memristors and implements competitive learning in a compact circuit module, and enables in-situ plasticity in the memristor synapses. We demonstrate handwritten-digits recognition using the proposed architecture using transistor-level circuit simulations. As the described neuromorphic architecture is homogeneous, it realizes a fundamental building block for large-scale energy-efficient brain-inspired silicon chips that could lead to next-generation cognitive computing.

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Section: Discussionmentioning

confidence: 99%

Homogeneous Spiking Neuromorphic System for Real-World Pattern Recognition

Saxena

Zhu

2015

IEEE J. Emerg. Sel. Topics Circuits Syst.

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“…In larger crossbars, the greater number of sneak paths makes it even more difficult to distinguish between the stored values. Various techniques have been proposed to reduce the sneak path effect, including multistage reading, diode gating, and transistor gating [22,[27][28][29]. In this paper, we focus on the row grounding technique, where unselected rows are grounded, as shown in Figure 2.…”

Section: Sneak Path In a Memristive Crossbar Arraymentioning

confidence: 99%

Analysis of the row grounding technique in a memristor‐based crossbar array

Dozortsev

Goldshtein

Kvatinsky

2017

Circuit Theory & Apps

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SUMMARYUsing memristive devices within a crossbar array could pave the way for memories with higher density and speed than state-of-the-art Flash memory, while maintaining relatively low energy. However, memristive crossbar arrays have great difficulty distinguishing logical states because of sneak path currents. The row grounding technique eliminates the sneak path effect, allowing reliable sampling of the memristor state.In this paper, we analyze the row grounding technique and propose several methods and constraints for the design of memristive crossbar arrays. When the row grounding technique is used for these arrays, our analysis shows that increasing the number of rows can help reduce read latency and energy, in contrast to the case of capacitive memory arrays. Simulation results confirm the theoretical analysis proposed in this paper.

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“…Depending on the resistance of these other cells, a sneak current I sneak may interfere with the ability of the external sensing circuitry that is trying to discern I target from I read . The sneak-path problem during the read operations can be eliminated by applying the read voltage to one of the lines, grounding the rest, and measuring the currents at the end of the lines [9], [21], as shown in Fig. 2(b).…”

Section: B Memristive-based Random-access Memoriesmentioning

confidence: 99%

“…Although it is possible to avoid the effect of the sneakpath problem during read operations on memristive-based crossbars [9], [21], the energy consumption and current requirements in the worst-case scenario while reading and writing impose design constrains that end up being the limiting factors for scaling.…”

Section: Introductionmentioning

confidence: 99%

HReRAM: A Hybrid Reconfigurable Resistive Random-Access Memory

Lastras-Montaño

Ghofrani

Cheng

2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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Abstract-Passive crossbar arrays of memristors have been identified as excellent alternatives for future random-access memories. One limitation is their inability of selecting a memory cell without the interference caused by the sneak-path currents from other partially selected cells, as it results not only in unnecessary waste of energy but also in larger current requirements. The complementary resistive switch (CRS), consisting in two anti-serially connected memristors, is considered a potential solution to the sneak-path problem. However, the destructive read operation and reduced endurance of the CRS render it unattractive for the otherwise excellent candidate for next-generation crossbar-based non-volatile memories. In this paper we explore the feasibility and tradeoffs of configuring part of the CRS memory into a memristive mode to mitigate these limitations. The inherent locality of memory accesses for most computer programs offers an opportunity for designing a cache-like adaptive CRS-based crossbar memory with hybrid configurations of CRS and memristive modes, enabling optimization for both endurance and energy consumption. Our simulation results validate that the proposed hybrid system achieves 1.5-7x reduction in energy consumption in comparison with a memristive-only memory system and significantly improves the endurance of the CRS-based memory. I. INTRODUCTIONPurely memristive non-volatile crossbar arrays are potential candidates as alternatives to existing non-volatile and volatile memories. Due to its unique characteristics, a memristor can provide better-than-NAND Flash storage densities with read and write operation speeds that are comparable to DRAM [17]. A purely memristive crossbar contains no active or select elements in the memory matrix, which makes it very competitive with other emerging memory technologies as well.Purely memristive crossbar arrays, however, suffer from an inherent sneak-path problem due to partially selected devices [21]. Although it is possible to avoid the effect of the sneakpath problem during read operations on memristive-based crossbars [9], [21], the energy consumption and current requirements in the worst-case scenario while reading and writing impose design constrains that end up being the limiting factors for scaling.The complementary resistive switch or CRS was proposed as a way to mitigate the sneak-path problem [8]. A CRS is formed by two anti-serially connected memristors and stores binary information as an internal configuration rather than as an actual resistance value, as done in a memristor. Both configurations in a CRS have a high resistance, which greatly reduces the data dependencies and parasitic current paths due to partially selected devices.In contrast to the non-destructive read operation of a single memristor [13], the read operation in a CRS is destructive by nature and must be followed by a restore, i.e., write operation [8]. This type of write amplification negatively affects the endurance of CRS-based memories and results in excessive energy...

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Memristor-based memory: The sneak paths problem and solutions

Cited by 381 publications

References 45 publications

Homogeneous Spiking Neuromorphic System for Real-World Pattern Recognition

Homogeneous Spiking Neuromorphic System for Real-World Pattern Recognition

Analysis of the row grounding technique in a memristor‐based crossbar array

HReRAM: A Hybrid Reconfigurable Resistive Random-Access Memory

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