2014 IEEE International Symposium on Circuits and Systems (ISCAS) 2014
DOI: 10.1109/iscas.2014.6865619
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Memristors-based Ternary Content Addressable Memory (mTCAM)

Abstract: A memristors-based Ternary Content Addressable Memory (mTCAM) is presented. A unit mTCAM cell consists of 5T2R, five transistors and two memristors to store the ternary information, having higher storage density than conventional CMOS TCAMs together with the memristors' unique nonvolatility. In the write mode, each memristor in the cell is programmed individually such that high impedance is always present between searchlines to reduce the direct current. A twostep write scheme is proposed to reduce the write v… Show more

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Cited by 10 publications
(5 citation statements)
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“…As introduced in the previous sections, the probability of error in searching the Re-TCAM can be defined as the probability of finding the full bit-line match resistance/voltage less than a predefined threshold based resistance/voltage or finding the one-mismatch bit-line resistance/voltage higher than that threshold. Figure 8 shows the variation of the probability of error (PoE R ) using the developed R th in Equation (26) and the variation of the probability of error (PoE R S ) using another resistance based-threshold defined as the geometric mean between R fm and R 1mm R th S = ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi R f m Á R 1mm p À Á . Clearly, for a particular W under a specific Tolerance, PoE R is less than PoE R S .…”
Section: Probability Of Error Analysismentioning
confidence: 99%
See 1 more Smart Citation
“…As introduced in the previous sections, the probability of error in searching the Re-TCAM can be defined as the probability of finding the full bit-line match resistance/voltage less than a predefined threshold based resistance/voltage or finding the one-mismatch bit-line resistance/voltage higher than that threshold. Figure 8 shows the variation of the probability of error (PoE R ) using the developed R th in Equation (26) and the variation of the probability of error (PoE R S ) using another resistance based-threshold defined as the geometric mean between R fm and R 1mm R th S = ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi R f m Á R 1mm p À Á . Clearly, for a particular W under a specific Tolerance, PoE R is less than PoE R S .…”
Section: Probability Of Error Analysismentioning
confidence: 99%
“…The designs differed in the numbers of memristors and transistors employed to constitute the bit‐cell memory in the CAM array. Different bit‐cell arrangements of possible Re‐TCAM structures with SRAM 8T‐2M (8‐Transistors 2‐memristors), 24 SRAM‐6T‐2M, 25 SRAM‐5T‐2M, 26 Re‐CAM‐5T‐2M, 27 and Re‐CAM‐2T‐2M 28 were introduced. The 2T2M bit‐cell design is perceived as the densest and efficient circuit topology, primarily for Re‐TCAM.…”
Section: Introductionmentioning
confidence: 99%
“…It greatly decreases the distance between logic and memory as well as increases the number of connections between them by merging several memory layers, approaching the realization of an intelligent system, which could have memory and logic merged. Table. III Performance comparison of TCAMs associated with different types of storage memories [28]- [30] …”
Section: Discussionmentioning
confidence: 99%
“…To overcome these obstacles, several studies proposed hybrid memristor-CMOS based TCAM using transistors as the comparison unit and emerging non-volatile memories as the storage element rather static random access memory (SRAM). [14][15][16][17][18][19][20][21][22] Compared with traditional CMOS-based TCAM, these hybrid designs have higher capacity and lower search energy.…”
Section: Introductionmentioning
confidence: 99%