Mesh Based Obfuscation of Analog Circuit Properties

Rao, Vaibhav Venugopal; Savidis, Ioannis

doi:10.1109/iscas.2019.8702671

Cited by 15 publications

(9 citation statements)

References 8 publications

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“…Two types of approaches can be found in the literature, namely expanding the biasing circuit [8]- [10], and the design of a standalone block that generates the desired bias [11], [12].…”

Section: State-of-the-art In A/m-s Ic Lockingmentioning

confidence: 99%

“…In [10], extending [8], a transistor is replaced with a number of parallel and series-connected transistors, thereby creating a mesh. Each transistor in the mesh is sized differently and is controlled with a key-bit.…”

Section: State-of-the-art In A/m-s Ic Lockingmentioning

confidence: 99%

“…These equations include the relationships between: (a) the obfuscated component value, e.g., the geometry of the mirror transistor in a current mirror, and the key-bits; (b) the bias and the obfuscated component value; and (c) the bias and the performances listed in the data-sheet. Two counterattacks are proposed in [17] that apply to the biasing locking techniques in [8]- [10]. The first exploits the key spacing, in particular the fact that there is an exclusion zone around the obfuscated parameter value, such that only the correct key produces values within this zone.…”

Section: B Counter-attacks On Lockingmentioning

confidence: 99%

“…In terms of area overhead, biasing locking techniques based on biasing circuit expansion [8]- [10] feature low area overhead, while memristor-based [11] and neural network-based [12] biasing require large on-chip resources. In [8], a 6% area overhead is reported when applying biasing locking to a PLL based on transistor width obfuscation.…”

Section: Techniquesmentioning

confidence: 99%

“…In terms of power overhead, biasing locking based on biasing circuit expansion [8]- [10] seems to provide the lowest power overhead. In [8], a 1% power overhead is reported when applying biasing locking to a PLL based on transistor width obfuscation.…”

Section: Mixlock (This Work) Mixed-signal Low Lowmentioning

confidence: 99%

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Digitally Assisted Mixed-Signal Circuit Security

Leonhard¹,

Limaye

Turk

et al. 2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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The design and manufacturing steps of a chip typically involve several parties. For example, a chip may comprise several third-party Intellectual Property (IP) cores and the Integrated Circuit (IC) fabrication may be outsourced to a third-party foundry. IP cores and ICs are shared with potentially untrusted third parties and, as a result, are subject to piracy attacks. Even more, any legally purchased chip may be reverse-engineered to retrieve the design down to transistorlevel and, thereby, it is also subject to piracy attacks. In this paper, we propose MixLock, an anti-piracy countermeasure for mixed-signal IP cores and ICs. MixLock protection is based on inserting a lock mechanism into the design such that correct functionality is established only after applying a key which is the designer's secret. The lock mechanism acts on the mixedsignal performances by leveraging logic locking of the digital part. MixLock presents several key attributes. It is generally applicable, it is non-intrusive to the sensitive analog section, it incurs no performance penalty and has very low area and power overheads, it is fully automated, and it is capable of co-optimizing security in both the analog and digital domains. We demonstrate MixLock on a Σ∆ Analog-to-Digital Converter (ADC) using hardware measurements and an audio demonstrator.

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“…Two types of approaches can be found in the literature, namely expanding the biasing circuit [8]- [10], and the design of a standalone block that generates the desired bias [11], [12].…”

Section: State-of-the-art In A/m-s Ic Lockingmentioning

confidence: 99%

Section: State-of-the-art In A/m-s Ic Lockingmentioning

confidence: 99%

Section: B Counter-attacks On Lockingmentioning

confidence: 99%

Section: Techniquesmentioning

confidence: 99%

Section: Mixlock (This Work) Mixed-signal Low Lowmentioning

confidence: 99%

See 3 more Smart Citations

Digitally Assisted Mixed-Signal Circuit Security

Leonhard¹,

Limaye

Turk

et al. 2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Anti-Piracy of Analog and Mixed-Signal Circuits in FD-SOI

Tlili¹,

Sayed

Mahmoud³

et al. 2022

2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)

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We propose an anti-piracy security technique based on locking for analog and mixed-signal circuits designed in FD-SOI. We show that obfuscating the body-bias voltages of tunable transistors is an effective way for inducing high functionality corruption. The obfuscation is achieved by constituting a secret key from the concatenation of the input digital codes of the body-bias generators that produce the correct body-bias voltages. We also propose a slight modification of the bodybias generator that increases prohibitively the time complexity of counter-attacks aiming at finding an approximate key. The proposed locking scheme is demonstrated on a Σ∆ modulator used in highly-digitized RF receiver architectures.

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