Metal Electrode/High-$k$ Dielectric Gate-Stack Technology for Power Management

Maximizing performance for higher K gate dielectrics

“…6. Subsequently, Narayanan and co-workers 60,61 and Lee et al 3,62 and learnt how to optimize the thickness of the high K and interfacial layer so that there was less reduction in carrier mobilities. They now fall just below the line due to the intrinsic remote phonon mechanism as is also shown in Fig.…”

“…First, unless the higher K oxide has an unusual phonon structure and unusually low defect densities, a finite thickness SiO 2 layer will always be needed to screen its effect. 62 Second, the idea that LaAlO 3 can be grown epitaxially on Si without an interfacial SiO 2 layer 20 is not so useful for FETs. Third, there should be effort to evaluate the higher K oxides oxides such as LaLuO 3 in FETs with mobility measurements, and not just in metalinsulator-metal capacitor structures.…”

Influence of High-k Gate Dielectric on Nanoscale DG-MOSFET

“…This degradation is mainly caused by the fringing fields either from the gate to the source/drain regions or from the source/drain to the channel region which weakens the gate control [7]. But these shortcomings to some extent can be overcome by taking the gate stack (GS) configuration, i.e., high-k dielectrics over SiO 2 layer [8][9][10][11]. By taking a thick layer of dielectric material over a thin SiO 2 layer keeping EOT constant significantly reduces the gate tunnelling current.…”

Off-state leakage current of nano-scaled MOSFETs with high-k gate dielectric

“…With the development of semiconductor technology, the physical size of MOSFET has been scaling down that has driven the performance enhancement of transistors in the last four decades, the numbers of state-of-the-art semiconductor chips has reached one billion per CPU [1] .…”