Methodology for I/O cell placement and checking in ASIC designs using area-array power grid

“…The values of parasitic and wire inductance and other technology parameters are from ITRS'97 roadmap [1], .18¨m. As for bump pitch, we use the scaling number from [5]. We set all !…”

Section: Experimental Results and Concluding Remarksmentioning

confidence: 99%

“…Similar to [5], the following equation gives the effective resistance (R) for pad transfer metal from a block to the power supply bump with ¤ ¦ ¥ and ¤ § being constants derived from simulation, where…”

Section: A Ir-drop Requirementmentioning

confidence: 99%

Floorplanning with power supply noise avoidance

Chen

Huang

Liu

et al. 2003

Proceedings of the 2003 Conference on Asia South Pacific Design Automation - ASPDAC

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Abstract-With today's advanced integrated circuits (ICs) manufacturing technology in deep submicron (DSM) environment, we can integrate entire electronic systems on a single chip (SoC). However, without careful power supply planning in layout, the design of chips will suffer from mostly signal integrity problems including IR-drop, § I noise, and IC reliability. Postroute methodologies in solving signal integrity problem have been applied but they will cause a long turn-around time, which adds costly delays to time-to-market. In this paper, we study the problem of power supply noise avoidance as early as in floorplanning stage. We show that the noise avoidance in power supply planning problem can be formulated as a constrained maximum flow problem and present an efficient yet effective heuristic to handle the problem. Experimental results are encouraging. With slight increase of total wirelength, we achieve almost no IR-drop requirement violation and 46.6% of improvement on § I noise constraint violation compared with a previous approach.

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“…Reference [11] offers some details of low-level rules for local I/O placement verification. The verification is performed one window at a time.…”

Section: Voltage Islandmentioning

confidence: 99%

Issues and strategies for the physical design of system-on-a-chip ASICs

Bednar¹,

Buffet²,

Darden³

et al. 2002

IBM J. Res. & Dev.

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The density and performance of advanced silicon technologies have made system-on-achip ASICs possible. SoCs bring together a diverse set of functions and technology features on a single die of enormous complexity. The physical design of these complex ASICs requires a rich set of functional elements that integrate efficiently with a set of design flows and tools productive enough to meet product requirements successfully, without consuming more time or design resources than a simpler design. The architecture described, including functional libraries and physical design conventions, enables the creation of multiple SoC ASIC designs from a common infrastructure that addresses silicon integration, electrical robustness, and packaging challenges. An implementation strategy follows from this design infrastructure that includes hierarchical design concepts, placement, routing, and verification processes.

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Methodology for I/O cell placement and checking in ASIC designs using area-array power grid

Cited by 19 publications

References 2 publications

Analyzing CUDA workloads using a detailed GPU simulator

Analyzing CUDA workloads using a detailed GPU simulator

Floorplanning with power supply noise avoidance

Issues and strategies for the physical design of system-on-a-chip ASICs

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