Methodology for multi-granularity embedded processor power model generation for an ESL design flow

Abstract

With power becoming a major constraint for multi-processor embedded systems, it is becoming important for designers to characterize and model processor power dissipation. It is critical for these processor power models to be useable across various modeling abstractions in an electronic system level (ESL) design flow, to guide early design decisions. In this paper, we propose a unified processor power modeling methodology for the creation of power models at multiple granularity levels that can be quickly mapped to an ESL design flow. Our experimental results based on applying the proposed methodology on an OpenRISC processor demonstrate the usefulness of having multiple power models. The generated models range from very high-level two-state and architectural/ISS models that can be used in transaction level models (TLM), to extremely detailed cycle-accurate models that enable early exploration of power optimization techniques. These models offer a designer tremendous flexibility to trade off estimation accuracy with estimation/simulation effort.

A basic-block power annotation approach for fast and accurate embedded software power estimation

“…ISS+BPA, runs at almost the same speed as the ideal functional ISS. Using the gate level power analysis tool PrimePower as a golden reference for accuracy comparison, we benchmark with ALPA, a well-known micro-architectural level power analysis approach [13] and instruction level power analysis (ILPA), on the same set of test cases. As shown in Figure 5, our error rate is three to ten times less than ALPA and the simulation speed is four orders faster, as shown in Table 1.…”

“…Although ILPA is useful for early average power estimation, it cannot do pipeline-accurate power estimation due to the lack of detailed information of pipeline behaviors. For example, the instruction level power model proposed in [13] for the OpenRISC processor gives more than 14% inaccuracy compared to gate level power estimation.…”

“…In contrast, Park et al [13] create a power contribution lookup table for processor modeling and accordingly generate multigranularity power models that range from coarse-grained (twostate, i.e. running state and sleeping state) to fine-grained (cycleaccurate) models.…”