Methodology for Performance Optimization in Noise- and Distortion-Canceling LNA

Martinez-Perez, Antonio D.; Gimeno, C.; Flandre, Denis; Aznar, Francisco; Royo, Guillermo; Sánchez-Azqueta, Carlos

doi:10.1109/smacd.2019.8795241

Cited by 4 publications

(6 citation statements)

References 6 publications

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“…The final design presents very competitive tradeoffs com-pared with similar designs from the literature (Table 3). In [2] the same topology is used, achieving better performance in terms of N F , IIP 3 and power, but slightly lower in terms of gain and bandwidth, at the cost of employing a more advanced and expensive technology (45-nm SOI CMOS).…”

Section: Resultsmentioning

confidence: 99%

“…Nonetheless, the methodology is not technology dependent. Indeed, Table 3 includes the results of a circuit designed by this methodology in other technologies, including SOI one [2].…”

Section: Discussionmentioning

confidence: 99%

“…The proposed methodology faces the challenge of optimizing the trade-off between specifications instead of improving each one separately. Thanks to a graphical representation of the design window, the designer can observe the reachable specifications and the relationship between the target parameters [2]. Thus, the work can aim for the most advantageous trade-off for their particular application, in other words, the best ad hoc optimization.…”

Section: Introductionmentioning

confidence: 99%

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Design-Window Methodology for Inductorless Noise-Cancelling CMOS LNAs

et al. 2022

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This paper presents an optimization methodology for inductorless noise-cancelling CMOS Low-Noise Amplifiers (LNA), whose performance typically depends on a tight balance in the design of two transistor stages. Due to the different functions of the two parts, noise-cancelling amplifiers become very difficult to analyze in detail by closed-form expressions or straight simulations: each section significantly affects the results of the other. In addition, opposed specifications, such as gain and cut-off frequency, suppose another grade of complexity due to the interplay of the two branches of the circuit. As a solution, the proposed methodology uses a visualization of the design window in 2-dimensional space to optimize the different parameters of the specifications without compromising the others. All specification constraints are represented in a single figure instead of one graph per parameter. Compared with most optimization methods, the design window methodology observes the design span instead of isolated design points that might not guarantee feasibility. Furthermore, as a simulation-driven exploration method, it benefits from complete device models with high-order effects that would be too complex to include in analytical expressions but critical to achieving maximum efficiency. As an example of the method, the paper describes the optimization of the well-known CS-CG noisecancelling LNA in 65-nm standard CMOS technology. Final post-layout simulations report very competitive results with a 3.7-dB noise figure, a 17-dB gain, and a cut-off frequency above 7 GHz.

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Section: Resultsmentioning

confidence: 99%

“…Nonetheless, the methodology is not technology dependent. Indeed, Table 3 includes the results of a circuit designed by this methodology in other technologies, including SOI one [2].…”

Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Design-Window Methodology for Inductorless Noise-Cancelling CMOS LNAs

et al. 2022

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“…The result can be graphically depicted in terms of the desired specifications by an isograph. In that representation, the space of W 1 -W 2 pairs that fulfil all specifications is the design window [6].…”

Section: Simulation Resultsmentioning

confidence: 99%

A New Approach to the Design of CMOS Inductorless Common-gate Low-noise Amplifiers

Martinez-Perez

Martinez-Martinez

Royo

et al. 2020

2020 European Conference on Circuit Theory and Design (ECCTD)

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This work proposes a new approach to design a simple and effective LNA reaching very competitive results in 1.2-V 65-nm standard CMOS technology. The proposed design uses a transconductance enhancement technique to achieve 2.3 dB of noise figure at the 5 GHz band. The paper exposes the advantages of a reduced number of devices in the circuit and analyses the topology. Simulations with complete technology models and statistical analysis are presented for more precise results.

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“…2 muestra el resultado del escenario final con la ventana de diseño en verde. En [4] puede encontrarse la metodología descrita en mayor detalle.…”

Section: Metodología De Diseñounclassified