Proceedings of the 2000 International Symposium on Physical Design 2000
DOI: 10.1145/332357.332383
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Methodology for repeater insertion management in the RTL, layout, floorplan and fullchip timing databases of the Itanium microprocessor

Abstract: In this paper, we describe a methodology for inserting repeaters into the RTL, Layout, Floorplan and Fullchip timing databases of the Itanium™ processor.

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Cited by 22 publications
(11 citation statements)
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“…The gains from this technique can be dramatic, as the clock frequencies are no longer restricted by the interconnect speed. In one reported case, Intel inserted thousands of flip-flops on the global wires of the Itanium™ processor and achieved up to 1.7 GHz operating frequency even under 0.18um technology [9]. ITRS [14] has also acknowledged this strategy by removing global clock cycle times from its 2001 and later roadmaps.…”
Section: Introductionmentioning
confidence: 99%
“…The gains from this technique can be dramatic, as the clock frequencies are no longer restricted by the interconnect speed. In one reported case, Intel inserted thousands of flip-flops on the global wires of the Itanium™ processor and achieved up to 1.7 GHz operating frequency even under 0.18um technology [9]. ITRS [14] has also acknowledged this strategy by removing global clock cycle times from its 2001 and later roadmaps.…”
Section: Introductionmentioning
confidence: 99%
“…(In industry, this idea was considered for Intel Itanium microprocessor design [6].) Our method adopts the simulated annealing mechanism to refine a general floorplan so that buffers can be inserted more effectively.…”
Section: Introductionmentioning
confidence: 99%
“…Previous work has shown that buffer insertion is an effective and widely used technique to improve interconnect delay, especially for global signals [1], [13]. (For example, over 85% of global nets in Intel Itanium microprocessors are buffered to reshape signals [9].) Because buffers consume silicon resource, it is too difficult to insert a large number of buffers individually after placement or routing when most silicon and routing resources are occupied.…”
mentioning
confidence: 99%
“…However, placing buffers inside macroblocks requires one to consider the interaction between logic and interconnect. Therefore, buffers are typically inserted outside macroblocks [9].…”
mentioning
confidence: 99%