Methodology to Implement Logic Controllers with both Reconfigurable and Programmable Hardware

Silva, C.F.; Quintans, C.; Mandado, Enrique; Castro, Manuel

doi:10.1109/isie.2007.4374620

Cited by 8 publications

(3 citation statements)

References 7 publications

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“…There is no analysis of the efficiency of such VHDL-based implementations on FPGAs. Silva et al (2007) describe an implementation of industrial control logic targeted at Altera FPGAs (hardware implementation) or Simatic PLC (software implementation). Petri nets are used to describe the design rather than Ladder Diagrams, so the implementations are not directly comparable.…”

Section: Ladder Diagramsmentioning

confidence: 99%

FPGA Implementations of Ladder Diagrams

Bergmann

Waldeck²,

Shukla³

2013

MAS

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The performance of programmable logic controllers is often constrained by the microprocessor and the real-time firmware of the controller. Field programmable gate arrays (FPGAs) are an attractive potential implementation medium for high-speed control because of their fast and parallel execution and programmable nature. Ladder Diagrams are a standard graphical programming method for industrial controllers, but compilers from Ladder Diagrams to FPGA hardware do not yet exist. This paper explores the comparative speed of four different classes of FGPA implementation of Ladder Diagrams -Interpreted Software, Compiled Software, Interpreted Hardware and Compiled Hardware. It also explores parallel versus serial execution of Ladder Diagrams in hardware, and identifies timers as a major resource user in parallel implementations. Overall, a Shared Timer Serial Compiled Hardware system for FPGA implementation of Ladder Diagrams is recommended. Using comparable FPGA resources to other alternatives it provides a 20-600 times speed improvement over other solutions whilst maintaining correct Ladder Diagram semantics.

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Section: Ladder Diagramsmentioning

confidence: 99%

FPGA Implementations of Ladder Diagrams

Bergmann

Waldeck²,

Shukla³

2013

MAS

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“…Ikeshita et al [8] presented a conversion program that translates sequential function chart (SFC) description into Verilog‐HDL for logic synthesis. Silva et al [9,10] presented a hardware–software platform to implement logic controllers with both PLC and FPGA, where Petri net descriptions are translated into VHDL codes.…”

Section: Background and Related Studiesmentioning

confidence: 99%

An FPGA implementation of hard‐wired sequence control system based on PLC software

Ichikawa

Akinaka

Hata

et al. 2011

IEEJ Transactions Elec Engng

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Although a programmable logic controller (PLC) has been widely adopted for the sequence control of industrial machinery, its performance does not always satisfy the recent requirements in large and highly responsive systems. With the state‐of‐the‐art field programmable gate array (FPGA) technology, it is possible to implement a control program with hard‐wired logic for higher response and reduced implementation cost/space. This approach is also worthwhile for transmigration of legacy PLC software into forthcoming FPGA‐based control hardware. This study presents a systematic method to implement a hard‐wired sequence control from PLC software. PLC instructions are converted into VHDL codes, and then implemented as logic circuit with various peripheral functions. Productive PLC programs were examined with Mitsubishi Electric FX2N PLC and Altera Stratix II FPGA, and were shown to fit into a common FPGA chip. A straightforward Sequential design was estimated to be 184 times faster than PLC, while a performance‐oriented Flat design was estimated to be 44 times faster than Sequential design (i.e., 8050 times faster than PLC). A practical perfect layer winder system was actually built and successfully operated with our FPGA control board, whose logic design was implemented with our tools. © 2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

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“…We should also mention two recent publications [16] and [17], which describe an integrated development system for producing VHDL code from Petri Net descriptions. This methodology focuses on classical automation tasks rather than computationally intensive applications and tries to increase the performance by implementing operations in parallel.…”

Section: Background and Related Workmentioning

confidence: 99%

An architectural exploration framework for efficient FPGA implementation of PLC programs

Economakos¹,

Economakos

2009

2009 17th Mediterranean Conference on Control and Automation

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This paper presents an automated framework for obtaining high-performance FPGA implementations of industrial automation and control algorithms coded as PLC programs. The proposed method is mainly targeting demanding applications, requiring lots of numerical computations. Based on previous experience, the proposed framework exploits Electronic System Level modeling methodologies and tools for high-level hardware synthesis. Since most of these tools are not compatible with PLC development environments, custom translating software built by using standard compiler techniques, can be employed for converting PLC programs to a form that can be understood by the selected tools. Furthermore, the translating software uses different coding templates to support microarchitectural level design trade-offs. Experimental results involving three wellknown industrial control algorithms show that appropriate coding styles can offer 2x performance improvements, being simple and syntactically similar to Statement List code.

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Methodology to Implement Logic Controllers with both Reconfigurable and Programmable Hardware

Cited by 8 publications

References 7 publications

FPGA Implementations of Ladder Diagrams

FPGA Implementations of Ladder Diagrams

An FPGA implementation of hard‐wired sequence control system based on PLC software

An architectural exploration framework for efficient FPGA implementation of PLC programs

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