Metrology for Monitoring and Detecting Process Issues in a TSV Module

Philipsen, Harold; Vandersmissen, K.; Cockburn, Andrew; Erickson, David; Drijbooms, C.; Moussa, Alain; Bender, Hugo; Struyf, Herbert

doi:10.1149/2.005406jss

Cited by 13 publications

(10 citation statements)

References 39 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Metallization of through-Si via (TSV) has been developed by using extended technique from BEOL interconnect, based on physical vapor deposition (PVD) barrier/seed and Cu electrochemical deposition [1]. However, the conventional PVD barrier/seed has been facing several challenges when applied in high aspect ratio features, such as insufficient coverage around bottom and the requirement of a thick Cu overburden (> 2 m) as shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

Cu seeding using electroless deposition on Ru liner for high aspect ratio through-Si vias

Inoue

Philipsen

Veen

et al. 2014

2014 International 3D Systems Integration Conference (3DIC)

Self Cite

View full text Add to dashboard Cite

High aspect ratio through-Si vias (AR=16.7) filling has been achieved by using non-PVD seed metallization approach. We demonstrate the formation of conformal and thin electroless deposited Cu seed on Ru liner. The optimized ELD Cu process was conducted at room temperature on activated Ru surface, which can improve the ELD bath life time. The deposited Cu with 2,2' bipyridyl shows smoother and higher purity inside the Cu film.

show abstract

Section: Introductionmentioning

confidence: 99%

Cu seeding using electroless deposition on Ru liner for high aspect ratio through-Si vias

Inoue

Philipsen

Veen

et al. 2014

2014 International 3D Systems Integration Conference (3DIC)

Self Cite

View full text Add to dashboard Cite

show abstract

“…[1][2][3][4][5][6] Among all of the filling materials, electroplated copper has been widely used for its well-known benefits such as high conductivity, low deposition temperature, and compatibility with backend of line (BEOL) processing. [7][8][9][10] Despite all these advantages, there is a great challenge concerned with the thermo-mechanical reliability of Cu-filled TSV. 11,12 Copper protrusion is one of these major reliability issues, caused by the mismatch of coefficient of thermal expansion (CTE) between copper film and silicon substrate.…”

mentioning

confidence: 99%

A View on Annealing Behavior of Cu-Filled Through-Silicon Vias (TSV)

Huang

Deng

et al. 2016

ECS J. Solid State Sci. Technol.

View full text Add to dashboard Cite

In this article, based on analyzing the effect of self-annealing of copper film both empirically and numerically, a new hypothesis has been proposed to better explain the mechanism of copper protrusion evolution with annealing temperature. Electroplated copper in TSV goes through an intense self-annealing process after deposition at room temperature. The effect of self-annealing, which has been all ignored to date, is critical to the annealing behavior of Cu-filled TSV. During self-annealing, a tensile stress field is generated in TSV due to the occurrence of the initial copper protrusion, and this tensile stress can strongly suppress the copper protrusion during annealing treatment. Atomic Force Microscope (AFM) has been used for the measurements of copper protrusion. A finite element model based on the hot deformation and self-annealing of copper film has been proposed to confirm the hypothesis.

show abstract

“…1,2 Since the electroplated copper has been introduced to TSV process of IC chips industry, copper is the most common material used in via filling. [3][4][5] In recent years, many articles have reported the successful void free copper filling of TSVs. 6,7 In addition, the annealing process to reduce the stress of the electroplated copper is essential for device reliability.…”

mentioning

confidence: 99%

The Influence of Annealing on Characteristics of Copper in TSV

Feng

Hang

2015

ECS J. Solid State Sci. Technol.

View full text Add to dashboard Cite

In this work, the through silicon via (TSVs) with 100 μm × 13 μm depth-to-width ratio after 300°C and 400°C annealing treatment were characterized respectively by electron backscattered diffraction (EBSD). Finite element modeling was used to demonstrate the Von Mises mechanical stress distribution of copper in TSV caused by different thermal expansion coefficient of copper and silicon at different temperature. According to the modeling results, the compressive yield strength of copper in our experiment is about 1 GPa. The Schmid factors results analyzed from EBSD data show the Schmid factors of copper grains in TSV are almost all larger than 0.3 and soft orientation both before and after annealing treatment. According to Schimd law, the plastic deformation occurs in the grains that have the highest Schmid factors. Schmid factor distribution in the range of 0.45–0.5 reduces in copper after 400°C annealing treatment. The textures of the as deposited copper are eliminated by the migration of 38.9°/110 twist boundaries mainly composed by Σ9 in both annealing treatments. Annealing at 400°C makes the deposited copper contains more 60°/111 coherent twin Σ3 boundaries that have lower energy than that of the copper annealed at 300°C.

show abstract

Metrology for Monitoring and Detecting Process Issues in a TSV Module

Cited by 13 publications

References 39 publications

Cu seeding using electroless deposition on Ru liner for high aspect ratio through-Si vias

Cu seeding using electroless deposition on Ru liner for high aspect ratio through-Si vias

A View on Annealing Behavior of Cu-Filled Through-Silicon Vias (TSV)

The Influence of Annealing on Characteristics of Copper in TSV

Contact Info

Product

Resources

About