Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations

Merchant, Farhad; Maity, Arka; Mahadurkar, Mahesh; Vatwani, Kapil; Munje, Ishan; Krishna, M. Ghanashyam; Nalesh, S; Gopalan, Nandhini; Raha, Soumyendu; Nandy, S. K.; Narayan, Ranjani

doi:10.1109/vlsid.2015.31

Cited by 14 publications

(21 citation statements)

References 23 publications

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“…Based on our case studies in dgemm, dgeqrf, and dgetrf it can be inferred that the performance attained in the latest multicore and GPGPU is hardly 50-52% even for highly parallel operations like dgemm. Due to this shortcoming of multicore and GPGPU, we choose a customizable platform for our implementation presented in [9] that is capable of achieving up to 74% of the theoretical peak in dgemm [9] [14].…”

Section: Performance Evaluation Of Dgeqrf Dgetrf and Dgemm On Multicmentioning

confidence: 99%

“…Coarse Grained Reconfigurable Architectures (CGRAs) have been active topic of research due to their power performance and flexibility [9]. CGRAs are capable of domain customization and they are targeted to achieve performance of Application Specific Integrated Circuits (ASICs) and flexibility of Field Programmable Gate Arrays (FPGAs) through presence of ASIC-like structures [14] [8].…”

Section: Introductionmentioning

confidence: 99%

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Achieving Efficient Realization of Kalman Filter on CGRA Through Algorithm-Architecture Co-design

Merchant

Vatwani

Chattopadhyay

et al. 2018

Applied Reconfigurable Computing. Architectures, Tools, and Applications

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In this paper, we present efficient realization of Kalman Filter (KF) that can achieve up to 65% of the theoretical peak performance of underlying architecture platform. KF is realized using Modified Faddeeva Algorithm (MFA) as a basic building block due to its versatility and REDEFINE Coarse Grained Reconfigurable Architecture (CGRA) is used as a platform for experiments since REDEFINE is capable of supporting realization of a set algorithmic compute structures at run-time on a Reconfigurable Data-path (RDP). We perform several hardware and software based optimizations in the realization of KF to achieve 116% improvement in terms of Gflops over the first realization of KF. Overall, with the presented approach for KF, 4-105x performance improvement in terms of Gflops/watt over several academically and commercially available realizations of KF is attained. In REDEFINE, we show that our implementation is scalable and the performance attained is commensurate with the underlying hardware resources 6 .

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Section: Performance Evaluation Of Dgeqrf Dgetrf and Dgemm On Multicmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Achieving Efficient Realization of Kalman Filter on CGRA Through Algorithm-Architecture Co-design

Merchant

Vatwani

Chattopadhyay

et al. 2018

Applied Reconfigurable Computing. Architectures, Tools, and Applications

Self Cite

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“…The focus of [28] is on emulation of systolic schedule for GR on REDEFINE and hence synthesis of systolic array on REDEFINE. Other optimizations on REDE-FINE CGRAs are also attempted in [111,112], firstly targeting algorithmic optimization which is then exploited for CGRA-based acceleration.…”

Section: Cgrasmentioning

confidence: 99%

“…A recently enhanced REDEFINE CGRA for NLA [112] shows comparable values for 65nm, and shows better performance density if scaled to 45nm with custom DOT product units, however no execution times for large matrices could be found. Based on the reported latencies for 60×60 and 120×120 data size running matrix multiplication in [112], the slowest variant of Layers performs 4.2× and 2.8× faster on a 64×64 and 128×128 data set.…”

Section: Redefinementioning

confidence: 99%

Modeling, analysis and exploration of layers: A 3D computing architecture

Rakossy

2014

2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)

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Current trends in architectural design require high-performance, low-power, flexible architectures that can adapt quickly onto the ever shifting and evolving application landscape. Finding the best architecture matching these stringent constraints is further limited by a short time-to-market window, which severely limits design exploration options. This work tackles these problems by proposing a different view on architectural flexibility, which can be exploited to achieve high energy-efficiency and performance instead of being traded off, by exploiting the advantages of reconfigurable architectures. Starting from a theoretical view, a methodology is produced for exploration of two different approaches in achieving high energy efficiency with two different architectural concepts: an architecture perfectly tuned to the application; and a new reconfigurable layered architecture, which can adapt its structure to match the application.

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“…Performance of the system involving such floating point operations and floating point functions depends on the attributes of the Floating Point Unit (FPU). Look-up table based methods are highly popular in realization of FPU due to their fast convergence to the end results [5] [6][7] [8]. These methods use binary adders, multipliers and priority encoders as basic building blocks along with pre-computed table look-ups for the computation of elementary operations and transcendental functions.…”

Section: Introductionmentioning

confidence: 99%

Efficient Realization of Table Look-Up Based Double Precision Floating Point Arithmetic

Merchant

Choudhary

Nandy

et al. 2016

2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID)

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In this paper we present different optimization techniques on look-up table based algorithms for double precision floating point arithmetic. Based on our analysis of different look-up table based algorithms in the literature, we re-engineer basics blocks of the algorithms (i.e. multiplier(s) and adder(s)) to facilitate area and timing benefits to achieve higher performance. We propose different look-up table optimization techniques for the algorithms. We also analyze trade-off in employing exact rounding (0.5ulp) (unit in the last place) in the double precision floating point unit. Based on performance and extensibility criteria we take algorithms proposed by Wong and Goto as a base case to validate our optimization techniques and compare the performance with other algorithms in the literature. We improve the performance (latency × area) of Wong and Goto division algorithm by 26.94%.

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Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations

Cited by 14 publications

References 23 publications

Achieving Efficient Realization of Kalman Filter on CGRA Through Algorithm-Architecture Co-design

Achieving Efficient Realization of Kalman Filter on CGRA Through Algorithm-Architecture Co-design

Modeling, analysis and exploration of layers: A 3D computing architecture

Efficient Realization of Table Look-Up Based Double Precision Floating Point Arithmetic

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