Micro-Transformer-Based Integrated Digital Isolator in 180/90 nm CMOS

Butuzov, Vladimir; Nazarenko, A E; Bocharov, Yuri; Kus, Oleg N.; Prokopyev, Vitaliy; Dmitriev, Nikita; Смирнов, Е. Т.; Smirnova, T. V.; Salynsky, Nikolay

doi:10.1109/sibcon.2019.8729578

Cited by 3 publications

(2 citation statements)

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“…In Table I and Eq. (6) (7), ENP stands for enable signal, Y is the output of the demodulator and Q is the revised output without the effect of dV/dt noise. The logic module is shown in Fig.…”

Section: The Proposed Dv/dt Noise Canceling Circuitmentioning

confidence: 99%

“…Signal is transmitted from low-side to high-side by coupling since there is no direct connection between those two sides. Inductively coupled isolation methods provide the isolation through on-chip micro-transformers [2,3,4,5,6,7,8], and capacitive-coupled isolation methods utilize on-chip SiO2 capacitor as isolation barrier [9,10,11,12]. More work and research were done in these methods.…”

Section: Introductionmentioning

confidence: 99%

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A dV/dt noise canceling circuit of capacitive-isolated gate drivers

Zhang

Liu

Quan

et al. 2022

IEICE Electron. Express

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For capacitive-isolated gate drivers, the pulse width distortion (PWD) and common mode transient immunity (CMTI) are vital factors to evaluate its performance. In this paper, an envelope detection circuit and a dV/dt noise canceling circuit of capacitive-isolated gate drivers is designed based on X-FAB 0.35μm CMOS process. With these structures, this gate driver alleviates PWD and improve CMTI. Spectre simulation results show that the gate driver achieves 200kV/μs CMTI with 50ns propagation delay and maximum 7.4ns PWD. Besides, it has better robustness to fabrication process and temperature variation than conventional methods.

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Section: The Proposed Dv/dt Noise Canceling Circuitmentioning

confidence: 99%