Microarchitectural simulation and control of di/dt-induced power supply voltage variation

Grochowski, Ed; Ayers, D.; Tiwari, Vivek

doi:10.1109/hpca.2002.995694

Cited by 69 publications

(86 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Grochowski et al [9] was one of the first to illustrate the criticality of di/dt and propose solutions from the perspective of architects. Their work showed that applications exhibit varying current characteristics in a large range and proposed a microarchitectural solution to improve current demands with a feedback control mechanism.…”

Section: Related Workmentioning

confidence: 99%

“…To achieve this goal, we include preemptive turn-on gating of ALU modules by pre-decoding instructions. In a typical RISC ISA, the opcode can be determined by observing the first few bits of the instruction, 9 allowing the processor to pre-decode this information simultaneously with the instruction fetch. In the case that an ALU instruction has been detected early on, it is used to override the decay counter turn-off request.…”

Section: Preemptive Alu Gatingmentioning

confidence: 99%

“…To counteract this issue, our queue-based controller can be used to generate multiple clock-gating domains for even a single monolithic module by merely repliSuch optimizations however are out of the scope of this work. 9 For example, Alpha and PowerPC ISA uses the prefix 6 bits for opcode.…”

Section: Enhanced Progressive Gating Of Large Modulesmentioning

confidence: 99%

“…Unlike prior techniques [9,14,15,20,21,22,23,24] that largely aim at providing chip-level di/dt control, our technique monitors and controls di/dt by leveraging spatial information of modules obtained from a given floorplan and its power-pin distribution. Inductive noise is highly dependent on the chip floorplan which determines the relative location of functional modules and their distance from the power-pins.…”

Section: Introductionmentioning

confidence: 99%

“…Conventionally, the worse-case current consumption can be profiled and gauged by exercising power virus programs [9]. These programs were written with a goal in mind -varying the execution behavior from extremely high activity to almost none for inducing drastic fluctuation of current demands to stress the power-delivery network.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design

Mohamood

Healy

Lim

et al. 2006

2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06)

View full text Add to dashboard Cite

Power delivery is a growing reliability concern in microprocessors as the industry moves toward feature-rich, powerhungrier designs. To battle the ever-aggravating power consumption, modern microprocessor designers or researchers propose and apply aggressive power-saving techniques in the form of clock-gating and/or power-gating in order to operate the processor within a given power envelope. These techniques, however, often lead to high-frequency current variations, which can stress the power delivery system and jeopardize reliability due to inductive noise (L di dt ) in the power supply network. To counteract these issues, modern microprocessors are designed to operate under the worst-case current assumption by deploying adequate decoupling capacitance. With the trend of lower supply voltage and increased leakage power and current consumption, designing a processor for the worst case is becoming less appealing.In this paper, we propose a new dynamic inductive-noise controlling mechanism at the microarchitectural level that will limit the on-die current demand within predefined bounds, regardless of the native power and current characteristics of running applications. By dynamically monitoring the access patterns of microarchitectural modules, our mechanism can effectively limit simultaneous switching activity of close-by modules, thereby leveling voltage ringing at local power-pins. Compared to prior art, our di/dt controller is the first that takes the processor's floorplan as well as its power-pin distribution into account to provide a finer-grained control with minimal performance degradation. Based on the evaluation results using 2D floorplans, we show that our techniques can significantly improve inductive noise induced by current demand variation and reduce the average current variability by up to 7 times with an average performance overhead of 4.0%.

show abstract

Section: Related Workmentioning

confidence: 99%

Section: Preemptive Alu Gatingmentioning

confidence: 99%

Section: Enhanced Progressive Gating Of Large Modulesmentioning

confidence: 99%