Microwave performance of optically fabricated T-gate thin film silicon-on-sapphire based MOSFET's

Houssaye, P.R. de la; Chang, Ching‐Wen; Offord, Bruce W.; Imthurn, G.; Johnson, Rob; Asbeck, P.M.; Garcia, G.A.; Lagnado, I.

doi:10.1109/55.790738

Cited by 31 publications

(14 citation statements)

References 10 publications

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“…12. In Table II, we can notice a very low gate resistance ͑1 ⍀͒, due to the T-gate structure 16 and multifinger architecture ͑six fingers of 100 m͒ of this transistor, which promotes a high f max . Moreover, the R SD resistance value, corresponding to the sum of drain and source resistances R D and R S , respectively, is 2.9 ⍀ ͑for W ϭ 6 ϫ 100 m), that is in accordance with the extracted value of R SD given in the previous section.…”

Section: Rf Measurementsmentioning

confidence: 96%

“…Consequently, these low-access-resistance values of R g and R sd result in low thermal noise that is essential for low-noise amplifier design. 16 The gate-source and gate-drain capacitances (C gs and C gd ) have lower values compared to a high resistivity separation by implantation of oxygen ͑SIMOX͒ CMOS technology ͑MICROX™͒. Hanes et al have obtained C gs ϭ 0.8 pF/mm and C gd ϭ 285 fF/mm for a 0.25 m ϫ (4 ϫ 50 m) n-channel transistor with a gate oxide thickness of 12 nm.…”

Section: Rf Measurementsmentioning

confidence: 99%

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Characterization of Silicon-on-Sapphire Material and Devices for Radio Frequency Applications

Munteanu¹,

Cristoloveanu²,

Rozeau³

et al. 2001

J. Electrochem. Soc.

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Recently fabricated silicon-on-sapphire ͑SOS͒ wafers show improved electrical properties. This was demonstrated by both wafer and device-level characterization, in a wide range of temperatures ͑from 20 to 400 K͒. We discuss Hall effect measurements in bare SOS wafers as well as transistor properties in n-and p-channels ͑mobility, threshold voltage, subthreshold swing, and leakage currents͒. The short-channel effects are investigated in terms of charge sharing, drain-induced barrier lowering and fringing fields. Nonstatic measurements reveal a very long drain current overshoot at low temperature. Additional radio frequency measurements show excellent performance in the microwave domain.The explosive development of mobile communications requires high-quality microwave circuits with increasingly higher levels of integration. Silicon-on-sapphire ͑SOS͒ technology has shown great potential for high-frequency/radio-frequency ͑rf͒ applications. As compared with modern silicon-on-insulator ͑SOI͒ materials ͑SI-MOX, Unibond͒, SOS offers numerous advantages, such as 1 1. A quasi-infinitely thick isolating Al 2 O 3 substrate, reducing microwave losses and making SOS an ideal candidate for integration of rf circuits for wireless communications.2. 30 times higher thermal conductivity in sapphire than in SiO 2 , which allows better thermal dissipation through the substrates and reduces self-heating effects. 2,3 3. Low carrier lifetime, leading to a reduced gain of the parasitic bipolar transistor ͓therefore improved breakdown voltage of complementary metal-oxide semiconductor ͑CMOS͒ circuits, attenuated floating-body effects, and shorter transients͔. 4 4. It is a low-cost technological process. SOS also features important advantages over bulk silicon, essentially lower junction capacitances, better radiation hardness, and higher density of integration. At present, the use of SOS technology becomes an attractive solution for considerably improving the performances of silicon rf-integrated circuits. 2 Indeed, SOS allows the elaboration of passive components, such as inductors, with good performances compared to that fabricated on silicon substrates. Johnson et al. have shown high self-resonant frequencies and high quality factors of inductors fabricated on sapphire substrate (Q peak ϭ 9.9 and f sr ϭ 7 GHz for L ϭ 5.4 nH). 5 In the past, the SOS technology was handicapped mainly by the low-volume production, strain effects affecting the carrier mobility, and poor quality of the Si/Al 2 O 3 interface. 6 As-grown Si films on sapphire contained also a high defect density. These drawbacks have been reduced thanks to a continuous improvement in the implantation process and solid-phase epitaxial regrowth. Consequently, SOS wafers with reasonable crystal quality, very thin films ͑ϳ100 nm͒ and 6-8 in. wafer size are now available.This paper presents a detailed investigation of the electrical properties in recent SOS materials and devices, at low and high temperatures and in the microwave regime. Characterization of As-Grown SOS Films by Ha...

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Section: Rf Measurementsmentioning

confidence: 96%

Section: Rf Measurementsmentioning

confidence: 99%

Characterization of Silicon-on-Sapphire Material and Devices for Radio Frequency Applications

Munteanu¹,

Cristoloveanu²,

Rozeau³

et al. 2001

J. Electrochem. Soc.

Self Cite

View full text Add to dashboard Cite

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“…Another concern with SOI is the poor thermal conductivity of the buried oxide layer, which will become particularly crucial with the integration of transmitter power amplifiers. Silicon-on-sapphire (SOS), in contrast, provides excellent crosstalk isolation and thermal conductivity as well, but still owes prove of large-scale manufacturability, even though this technology has been around for a long time [6]. The concern of large-area consumption of on-chip passives [ Fig.…”

Section: (A)-(d)mentioning

confidence: 99%

IC-compatible two-level bulk micromachining process module for RF silicon technology

Pham

Sarro

et al. 2001

IEEE Trans. Electron Devices

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Abstract-This paper presents a novel two-level silicon bulk micromachining for integration of radio-frequency (RF) devices. The RF devices are fabricated at the frontside of Si (100) wafers using conventional integrated circuit (IC) technology. A post-processing module is applied from the wafer backside with precise alignment to the frontside. This module can provide a blanket ground plane at an optimum position beneath the wafer surface, a frontside contact from the wafer surface to that ground plane, and trenches to suppress crosstalk through the conductive silicon by adding two mask levels. An extension to four masks allows for an integration of large passive components beneath circuitry for a much reduced chip area, lowering chip size and cost. The feasibility of the novel post-process module is demonstrated through the fabrication of microstrip transmission lines, conductor-backed spiral inductors, trench-barriers against crosstalk through the conductive silicon substrate, and high-quality subsurface spiral inductors.

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“…In this work, the probe pad was modeled as C p1 parallel to (C p2 ϩR p ) and these three parameters were extracted from the measured s-parameter data of dummy pads. 1,11 One involves metal-reinforced gates and the other employs multifinger gates. The impact of gate resistance affects not only the overall noise performance of the devices but also the maximum oscillation frequency ( f max ).…”

Section: Comparison With Experimentsmentioning

confidence: 99%

Direct calculation of metal–oxide–semiconductor field effect transistor high frequency noise parameters

Chen

Deen

1998

Journal of Vacuum Science &Amp; Technology A: Vacuum, Surfaces, and Films

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Articles you may be interested inHigh frequency and noise model of gate-all-around metal-oxide-semiconductor field-effect transistors J. Appl. Phys. 105, 074505 (2009); 10.1063/1.3093884 High-frequency compact analytical noise model for double-gate metal-oxide-semiconductor field-effect transistor J. Appl. Phys. 105, 034510 (2009); 10.1063/1.3077279Low-frequency noise overshoot in ultrathin gate oxide silicon-on-insulator metal-oxide-semiconductor field-effect transistors Appl.Origin of microwave noise from an n-channel metal-oxide-semiconductor field effect transistor J. Appl. Phys. 92, 6679 (2002); 10.1063/1.1518763Direct extraction of the channel thermal noise in metal-oxide-semiconductor field effect transistor from measurements of their rf noise parameters This article presents, for the first time, a method to directly calculate the noise parameters ͑minimum noise figure NF min , equivalent noise resistance R n , and optimized source resistance R opt and reactance X opt ͒ of metal-oxide-semiconductor field effect transistors based on the HSPICE level 3 model because all the model parameters are available from the manufacturer of our device-under-test. All physically based high frequency noise sources, thermal noise from the channel, gate, source and drain resistances, induced gate noise, and the correlation among them, are considered, and the impact of gate resistance and induced gate noise on the noise parameters is studied. The method of direct calculation of noise parameters can be applied to any sophisticated small-signal device model.

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Microwave performance of optically fabricated T-gate thin film silicon-on-sapphire based MOSFET's

Cited by 31 publications

References 10 publications

Characterization of Silicon-on-Sapphire Material and Devices for Radio Frequency Applications

Characterization of Silicon-on-Sapphire Material and Devices for Radio Frequency Applications

IC-compatible two-level bulk micromachining process module for RF silicon technology

Direct calculation of metal–oxide–semiconductor field effect transistor high frequency noise parameters

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