MIM Capacitor Integration for Mixed-Signal/RF Applications

Ng, C.H.; Ho, Chaw-Sing; Chu, S.-F.; Sun, Shi-Chung

doi:10.1109/ted.2005.850642

Cited by 100 publications

(31 citation statements)

References 31 publications

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“…Compared with other integrated capacitor technologies, such as the polysilicon/silicon-based trench capacitors [7], [8] and crown-shaped capacitors [9], or the native intrametal lateral flux capacitors [10], [11] (also known as metal-oxide-metal capacitors), MIM capacitors offer lower resistive loss, lower substrate coupling noise, no charge depletion-induced voltage dependence, higher self resonance, and moderately high capacitance density [2]. However, as the capacitance density requirements stated in the latest 2011 International Roadmap for Semiconductors (ITRS) [12] continue to increase, further thinning of the dielectric layer tends to lead to excessive leakage currents and dielectric loss, thus either opting for high-k dielectric materials [13]- [16] or migrating to multilayer stacked structures [2] cannot be avoided. Yet, high-k dielectrics tend to exhibit permittivity with higher bias voltage dependence, whereas multilayer stacking will inevitably increase the complexity and cost of the fabrication due to the repetitive photolithography and etching steps, resulting in a tradeoff between capacitance density, performance, and low-cost manufacturing.…”

Section: Increased Multilayer Fabrication and Rfmentioning

confidence: 99%

Increased Multilayer Fabrication and RF Characterization of a High-Density Stacked MIM Capacitor Based on Selective Etching

Tseng

Xie

2014

IEEE Trans. Electron Devices

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This paper presents the fabrication and characterization of a high-density multilayer stacked metal-insulator-metal (MIM) capacitor based on a novel process of depositing the MIM multilayer on pillars followed by polishing and selective etching steps to form a stacked capacitor with merely three photolithography steps. In this paper, the pillars were made of glass to prevent substrate loss, whereas an oxide-nitride-oxide dielectric was employed for lower leakage, better voltage/frequency linearity, and better stress compensation. MIM capacitors with six dielectric layers were successfully fabricated, yielding capacitance density of 3.8 fF/μm 2 , maximum capacitance of 2.47 nF, and linear and quadratic voltage coefficients of capacitance below 21.2 ppm/V and 2.31 ppm/V 2 . The impedance was measured from 40 Hz to 3 GHz, and characterized by an analytically derived equivalent circuit model to verify the radio frequency applicability. The multilayer stacking-induced plate resistance mismatch and its effect on the equivalent series resistance (ESR) and effective capacitance was also investigated, which can be counteracted by a corrected metal thickness design. A low ESR of 800 m was achieved, whereas the self-resonance frequency was >760 MHz, successfully demonstrating the feasibility of this method to scale up capacitance densities for high-quality-factor, high-frequency, and large-value MIM capacitors.Index Terms-Capacitance density, equivalent series resistance (ESR), metal-insulator-metal (MIM) capacitor, multilayer stack, polishing, radio frequency (RF) passive device model, selective etching.

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Section: Increased Multilayer Fabrication and Rfmentioning

confidence: 99%

Increased Multilayer Fabrication and RF Characterization of a High-Density Stacked MIM Capacitor Based on Selective Etching

Tseng

Xie

2014

IEEE Trans. Electron Devices

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“…To provide effective decoupling above several hundreds of MHz, the total capacitance of the on-chip capacitors must be increased without increasing the chip area. Capacitors suitable for implementing such a decoupling solution on chips are metal oxide semiconductor (MOS) capacitors, metal-insulator-metal (MIM) capacitors, and deep trench (DT) capacitors [1][2][3]. MOS capacitors have been the most popular choice for the decoupling solution.…”

Section: Decoupling Capacitor Schemesmentioning

confidence: 99%

“…As silicon technology continues to scale, the deep-trench capacitors with high capacitance densities can be developed. For example, 65 nm CMOS technology can provide up to 200 nF/ mm 2 . DT capacitors that are realized on silicon chips as MOS decoupling capacitors offer better capacitance density, while the leakage current is much lower compared to MOS decoupling capacitors.…”

Section: Deep Trench Capacitormentioning

confidence: 99%

TSV Decoupling Schemes

Song

Pak

Kim

2014

Electrical Design of Through Silicon Via

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Three-dimensional (3D) through silicon via (TSV) technologies promise increased system integration at lower cost and reduced footprint, as well as increased system bandwidth. Three-dimensional TSV may be implemented by simply adapting current silicon fabrication and package technologies. There is a strong demand for 3D, high-density and the heterogeneous integration of silicon and passive components because 3D integrated circuit (3D ICs) increase layout complexity due to the needs for additional solution space, as well as increased power density and power noise issues. To overcome the I/O speed limitation related to the above power problems in 3D ICs, on-chip decoupling capacitors and passive components used in the packaging have been implemented using TSV technologies. In this chapter, TSV decoupling schemes are introduced, showing that they have prominent advantages relative to reducing the inductive power distribution network (PDN) impedance and suppressing power noise such as the simultaneously switching noise (SSN) in the 3D ICs.

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“…M ETAL-INSULATOR-METAL (MIM) capacitors have been widely used for digital, analog, mixed signal, and RF circuits [1], [2]. For device scaling, their capacitance density should be increased more than 10-15 fF/µm 2 with a tight requirement for leakage current (< 10 −8 A/cm 2 ) [3].…”

Section: Introductionmentioning

confidence: 99%

Capacitance Analysis of Highly Leaky $\hbox{Al}_{2} \hbox{O}_{3}$ MIM Capacitors Using Time Domain Reflectometry

Kim

Lee

Kim

et al. 2012

IEEE Electron Device Lett.

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Characterization of metal-insulator-metal (MIM) capacitors with a scaled dielectric is a challenge using conventional capacitance-voltage (C-V ) measurements due to a high leakage current. In this letter, a method to analyze MIM capacitance that is more immune to the leakage current problem has been successfully demonstrated using time domain reflectometry (TDR). The TDR method can be applied to Al 2 O 3 MIM capacitors with a capacitance density up to ∼11.1 fF/µm 2 , for which an impedance analyzer has failed to measure capacitance at 1 MHz. Differences in the voltage coefficient of capacitance and dielectric constant (k) were also investigated.Index Terms-Capacitance, metal-insulator-metal (MIM) capacitor, time domain reflectometry (TDR), voltage coefficient.

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MIM Capacitor Integration for Mixed-Signal/RF Applications

Cited by 100 publications

References 31 publications

Increased Multilayer Fabrication and RF Characterization of a High-Density Stacked MIM Capacitor Based on Selective Etching

Increased Multilayer Fabrication and RF Characterization of a High-Density Stacked MIM Capacitor Based on Selective Etching

TSV Decoupling Schemes

Capacitance Analysis of Highly Leaky $\hbox{Al}_{2} \hbox{O}_{3}$ MIM Capacitors Using Time Domain Reflectometry

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