Mismatch-tolerant time amplifier with embedded self-calibration

Lai, Jung-Chin; Hsu, Terng-Yin

doi:10.1109/icce-berlin.2015.7391289

Cited by 3 publications

(1 citation statement)

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“…When the SR latch starts up [24], [25], TA IN1 and TA IN2 are in the 0 state; S1 (and S2) and R1 (and R2) are in the 1 state; passing by the XOR gates, the OUTs (TA OUT1 and TA OUT2 ) are in the 0 state. The input pulse T IN is generated when TA IN1 and TA IN2 sequentially transition from 0 to 1 to make up the interval of time.…”

Section: Introductionmentioning

confidence: 99%

All-Digital Mismatched Calibrator and Compensator for SR Latch-Based Variable-Gain Time Amplifier

Chao¹,

Lai²,

Hsu³

2020

IEEE Access

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Two major mismatches in SR latch-based time amplifiers (TA) include input skew, which causes gain imbalance, and loading mismatch, which reduces gain accuracy. Accordingly, we propose an all-digital mismatched self-calibrator and compensator for an SR latch-based variable-gain TA. Tunable matching cells and variable capacitors are built into TAs to compensate for input skew (gain imbalance) and loading mismatch (gain inaccuracy). To ensure that the proposed calibration works efficiently and accurately, the TA must provide at least high and low gains where the low gain calibrates the most significant bit (MSB) and the high gain calibrates the least significant bit (LSB). This self-calibrator costs 4375 gates, and the power consumption is 2.8 mA for the TA gain with 2 and 3.2 mA for the TA gain with 16 at a sampling rate of 10 MHz. INDEX TERMS Mismatch calibration, self-calibration, time amplifier.

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Section: Introductionmentioning

confidence: 99%