Mitigating effects of non-ideal synaptic device characteristics for on-chip learning

Scaling-up resistive synaptic arrays for neuro-inspired architecture: Challenges and prospect

“…When scaling up the array size, the non-ideal device properties and array parasitics may potentially degrade the learning accuracy [8]. The non-ideal properties of the realistic devices today include a finite weight precision, a nonlinearity in weight update (conductance vs. #pulse), limited on/off ratio and device variations, see device examples ( Fig.…”

Li‐Ion Synaptic Transistor for Low Power Analog Computing

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Despite the possibility of tremendous gains in energy efficiency and numerous reports of resistance switching behavior in a range of materials systems, to date no memristor-based crossbar architecture has emerged as a clear competitor to CMOS or reached the energy efficiency of the brain. However, both device types currently suffer from several performance limitations that reduce their accuracy, scalability, and energy efficiency: excessive "write" noise, [16][17][18] "write" nonlinearities, [12,[19][20][21][22] and high switching voltages and currents. However, both device types currently suffer from several performance limitations that reduce their accuracy, scalability, and energy efficiency: excessive "write" noise, [16][17][18] "write" nonlinearities, [12,[19][20][21][22] and high switching voltages and currents.

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“…For Figure 2b,e, G 0 spans the range of 150-250 µS for −4.1 < OCP < −3.0 V. Here, we have plotted 40 counts (black) at every starting conductance point G 0 in order to measure the probability distribution about the mean change in conductance ΔG M . [22] An ideal resistive memory device should have a narrow distribution that is centered about single value of ΔG M over the entire range in G 0 . [22] An ideal resistive memory device should have a narrow distribution that is centered about single value of ΔG M over the entire range in G 0 .…”

Resistive Memory‐Based In‐Memory Computing: From Device and Large‐Scale Integration System Perspectives

“…However, the RRAM device uniformity and the large overhead of training circuits remain major challenges. [72,77] Some theoretical memristor models reason that nonlinearity is natural and derivable; however, the nonideal linear update can be mitigated by relaxing the strong requirements of training. Here, the symmetric weight update (Figure 3a) denotes the scenario where identical electrical excites result in the same amount change in weight Δw, during both SET and RESET programming.…”

“…[29,71] Considering the implementation complexity of training circuitry, the devices featuring linear and symmetric synaptic weight updates are more preferred. [72] For example, Chen et al presented the self-rectifying TaO x /TiO 2 RRAM, which is only %3% away from linearity during programming. The linear weight update means that the weight change Δw has linear dependency on the electrical excites, regardless of the current resistance state.…”