Mixed-signal 0.18μm CMOS and SiGe BiCMOS foundry technologies for ROIC applications

Kar‐Roy, A.; Howard, David; Racanelli, M.; Scott, Mike; Hurwitz, P.; Zwingman, R.; Chaudhry, S.; Jordan, Scott

doi:10.1117/12.865173

Cited by 6 publications

(2 citation statements)

References 14 publications

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“…CMOS foundries are beginning to offer integrated vias, making this a viable near-term approach. 12 The vertical interconnect density can be further reduced. Figure 9a and 9b shows a cross-section of a die stack integrated using Cu-Cu thermocompression bonds at 5-μm pitch.…”

Section: Scaling Of 3d Integration Technology To 10 Micron and Smallementioning

confidence: 99%

Advances in three-dimensional integration technologies in support of infrared focal plane arrays

et al. 2015

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Staring infrared focal plane arrays (FPAs) require pixel-level, three-dimensional (3D) integration with silicon readout integrated circuits (ROICs) that provide detector bias, integrate detector current, and may further process the signals. There is an increased interest in ROIC technology as a result of two trends in the evolution of infrared FPAs. The first trend involves decreasing the FPA pixel size, which leads to the increased information content within the same FPA die size. The second trend involves the desire to enhance signal processing capability at the FPA level, which opens the door to the detector behaving like a smart peripheral rather than a passive component-with complex signal processing functions being executed on, rather than off, the FPA chip. In this paper, we review recent advances in 3D integration process technologies that support these key trends in the development of infrared FPAs. Specifically, we discuss approaches in which the infrared sensor is integrated with 3D ROIC stacks composed of multiple layers of silicon circuitry interconnected using metal-filled through-silicon vias. We describe the continued development of the 3D integration technology and summarize key demonstrations that show its viability for pixels as small as 5 microns.

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Section: Scaling Of 3d Integration Technology To 10 Micron and Smallementioning

confidence: 99%

Advances in three-dimensional integration technologies in support of infrared focal plane arrays

et al. 2015

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“…Surrogates for analog IC wafers were of the siliconon-insulator (SOI) type to emulate a ROIC implemented in a thick film SOI CMOS process. 21,22) The thickness of the top Si and the buried oxide (BOX) layers in the SOI wafers were 15 and 2 µm, respectively. For the purpose of the proofof-concept demonstration, TSVs were fabricated in-house, whereas in the ultimate implementation the TSV module will be executed by a CMOS foundry.…”

Section: Fabrication Of Interconnect Arraysmentioning

confidence: 99%

Scaling of three-dimensional interconnect technology incorporating low temperature bonds to pitches of 10 µm for infrared focal plane array applications

Temple

Lueck

Malta

et al. 2015

Jpn. J. Appl. Phys.

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This paper focuses on the application of low temperature bonding to the fabrication of three-dimensional (3D) massively parallel signal processors for high performance infrared imagers. We review two generations of the 3D heterogeneous integration process. The first generation process, compatible with pixel sizes in the 20 to 30 µm range, relies on low temperature epoxy bonding that is followed by the formation of copper-filled through-silicon vias (TSVs). The second generation process, scalable to pixel sizes of 10 µm and smaller, employs solid–liquid diffusion bonding of copper–tin to copper at 250 °C; the bonding follows TSV fabrication. To demonstrate the second generation process, we fabricated 3D test vehicles in the form of 640 × 512 arrays of vertical interconnects composed of TSVs and metal–metal bonds on a 10 µm pitch. We characterized electrical conductivity of the interconnects, the isolation resistance between the interconnects, and the operability and yield of the arrays. The successful demonstration of the interconnect technology paves the way to a functional demonstration of 3D signal processors in infrared imagers with 10 µm pixels.

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Effectiveness of SEL Hardening Strategies and the Latchup Domino Effect

Dodds

Hooten

Reed

et al. 2012

IEEE Trans. Nucl. Sci.

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Mixed-signal 0.18μm CMOS and SiGe BiCMOS foundry technologies for ROIC applications

Cited by 6 publications

References 14 publications

Advances in three-dimensional integration technologies in support of infrared focal plane arrays

Advances in three-dimensional integration technologies in support of infrared focal plane arrays

Scaling of three-dimensional interconnect technology incorporating low temperature bonds to pitches of 10 µm for infrared focal plane array applications

Effectiveness of SEL Hardening Strategies and the Latchup Domino Effect

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